David Harris
53baf3e787
Cleaning shifter
2021-12-18 09:43:09 -08:00
David Harris
ebcffcdebd
Moved W64 truncation after result mux
2021-12-18 09:27:25 -08:00
David Harris
23c6b6370f
Forwarding logic factoring
2021-12-18 05:40:38 -08:00
David Harris
10dfefa8ad
Simplified FWriteInt interfaces by merging into RegWrite
2021-12-18 05:36:32 -08:00
David Harris
aebd746e71
Renamed MemAdrE to IEUAdrE and moved the MemAdrM flop from IEU to LSU to reduce wires crossing hierarchies
2021-12-15 12:10:45 -08:00
David Harris
4e35736e90
IEU cleanup:
2021-12-15 11:38:26 -08:00
David Harris
2d24230093
ALU and datapath cleanup
2021-12-14 11:15:47 -08:00
David Harris
2039752740
Simplified ALU and source multiplexers pass tests
2021-12-13 07:57:38 -08:00
David Harris
a1f8f7babe
Refactored IEU/ALU logic
2021-12-08 13:48:04 -08:00
David Harris
e14eb9872e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-08 12:33:59 -08:00
David Harris
d936342c97
Refactoring ALU and datapath muxes
2021-12-08 12:33:53 -08:00
Noah Limpert
15bdf5680e
removed .* instantiation from ieu.sv and datapth.sv in ieu folder
2021-12-08 00:24:27 -08:00
Kip Macsai-Goren
7a8c21e71f
renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv
2021-11-17 10:53:17 -08:00
David Harris
8287a1ef3e
Synchronous reset in non-flop blocks
2021-10-26 08:30:35 -07:00
David Harris
61fdb3d902
random lint cleanup
2021-10-23 11:24:36 -07:00
David Harris
8d9efcbafb
IEU cleanup
2021-10-23 11:13:28 -07:00
David Harris
4bf823e063
lint cleanup
2021-10-23 11:03:28 -07:00
David Harris
d570df864f
IEU lint cleanup
2021-10-23 10:51:53 -07:00
David Harris
8e516e6391
Lint cleanup from wallypipeliendhart
2021-10-23 10:29:52 -07:00
David Harris
d24bece3a8
Lint cleanup
2021-10-23 09:58:52 -07:00
David Harris
b3bded9e6c
Added more pipeline stage suffixes to divider
2021-10-02 22:54:01 -04:00
David Harris
e11c565a6f
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-30 23:15:34 -04:00
bbracker
6aa79657ed
Revert "first attempt at verilog side of checkpoint functionality"
...
This reverts commit fec96218f6
2021-09-30 20:45:26 -04:00
David Harris
caa36f267d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-30 20:07:43 -04:00
David Harris
42d573be57
SRT Division unsigned passing Imperas tests
2021-09-30 12:17:24 -04:00
bbracker
fec96218f6
first attempt at verilog side of checkpoint functionality
2021-09-28 23:17:58 -04:00
David Harris
9ae25b0cea
Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
2021-09-15 13:14:00 -04:00
Ross Thompson
551e3491af
Moved the ReadDataW register into the datapath.
...
The StallW from the hazard unit controls this.
Previously it was in the dcache and controlled by both the HPTW and hazard unit.
This caused an issue when the CPU expected the data to stay constant while
stalled, but the HPTW was causing the data to be modified.
2021-07-22 14:52:03 -05:00
Ross Thompson
fa26aec588
Merge branch 'main' into dcache
2021-07-15 11:55:20 -05:00
Katherine Parry
f5bfdf46db
fpu unpacking unit created
2021-07-14 17:56:49 -04:00
Ross Thompson
afc1bc9c38
Moved StoreStall into the hazard unit instead of in the d cache.
2021-07-13 13:20:50 -05:00
David Harris
9de97c1e20
Fixed busybear by restoring InstrValidW needed by testbench
2021-07-13 14:17:36 -04:00
Ross Thompson
47e16f5629
Fixed back to back store issue.
...
Note there is a bug in the lsuarb which needs to arbitrate a few execution stage signals.
2021-07-13 12:46:20 -05:00
David Harris
b5dddec858
Fixed InstrValid from W to M stage for CSR performance counters
2021-07-13 13:19:13 -04:00
Ross Thompson
ec80cc1820
Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented.
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Also faults and the dcache ptw interlock are not implemented.
2021-07-09 15:16:38 -05:00
David Harris
b23192cf1b
Gave names to for loops in generate blocks for ease of reference
2021-07-04 18:52:16 -04:00
Ross Thompson
dbd33465e1
Merge branch 'main' into bigbadbranch
2021-07-02 11:52:26 -05:00
Katherine Parry
0c2b7a1132
FPU control signals changed and FMA works
2021-06-28 18:53:58 -04:00
bbracker
34dbad967d
ah merge; I checked and this does pass all of regression except lints
2021-06-25 07:37:06 -04:00
bbracker
192171826b
changed SC M-to-E fowarding to W-to-E forwarding to improve critical path
2021-06-25 07:18:38 -04:00
Katherine Parry
7e3483b283
FPU forwarding reworked pt.1
2021-06-24 18:39:18 -04:00
bbracker
2155a4e485
Revert "fixed forwarding"
...
This reverts commit 86e369df52
2021-06-24 17:39:37 -04:00
bbracker
86e369df52
fixed forwarding
2021-06-24 11:20:21 -04:00
Ross Thompson
9b8bcb8e57
Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two.
...
Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB.
Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP.
With Kip.
2021-06-23 16:43:22 -05:00
David Harris
01d6ca1e2a
Fixed lint WIDTH errors
2021-06-09 20:58:20 -04:00
bbracker
2c77a13c08
fixed InstrValid signals and implemented less costly MEPC loading
2021-06-02 10:03:19 -04:00
Katherine Parry
1459d840ed
All compare instructions pass imperas tests
2021-05-27 15:23:28 -04:00
Katherine Parry
90d5fdba04
FMV.X.D imperas test passes
2021-05-24 14:44:30 -04:00
Katherine Parry
06af239e6c
FMV.D.X imperas test passes
2021-05-20 22:17:59 -04:00
bbracker
8a7fc959eb
small synthesis fixes
2021-05-04 15:21:01 -04:00
