bbracker fec96218f6 first attempt at verilog side of checkpoint functionality		2021-09-28 23:17:58 -04:00
..
alu.sv	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
controller.sv	Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.	2021-09-15 13:14:00 -04:00
datapath.sv	Moved the ReadDataW register into the datapath.	2021-07-22 14:52:03 -05:00
extend.sv	small synthesis fixes	2021-05-04 15:21:01 -04:00
forward.sv	ah merge; I checked and this does pass all of regression except lints	2021-06-25 07:37:06 -04:00
ieu.sv	Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.	2021-09-15 13:14:00 -04:00
regfile.sv	first attempt at verilog side of checkpoint functionality	2021-09-28 23:17:58 -04:00
shifter.sv	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00