Ross Thompson
3b31d8f8fb
Updated debug2 ila signal names.
2022-01-28 11:43:49 -06:00
Ross Thompson
840e814e95
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-25 19:21:04 -06:00
Ross Thompson
bb11f5637c
Added comport.setup to remind how to configure com port for xilinx fpga.
...
Added load-deadlock.tsm to trigger load operation deadlock.
2022-01-25 14:54:38 -06:00
David Harris
07425369fc
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
David Harris
6febce0001
Moved Dcache into bus block
2022-01-15 00:39:07 +00:00
Ross Thompson
0f14d2ec88
Added advanced Vivado debug scripts.
2022-01-07 17:56:40 -06:00
David Harris
b36ace221e
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
Ross Thompson
a11597b6bd
Added more debugging code for FPGA.
2021-12-17 14:40:25 -06:00
Ross Thompson
6d2a4b8354
Oups missed files in the last commit.
2021-12-15 10:25:08 -06:00
Ross Thompson
af9f97454d
Cleaned up fpga synthesis script.
2021-12-13 18:26:54 -06:00
Ross Thompson
68745d40f2
Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language.
2021-12-12 17:21:44 -06:00
Ross Thompson
29743c5e9e
Fixed two issues.
...
First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly.
Second the bidir buffer for the sd card was connected backwards.
2021-12-07 12:15:50 -06:00
Ross Thompson
c3c9c327b7
Fixed more constraint issues in fpga.
...
Added back in the ILA.
Design does not work yet. Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
2021-12-05 15:14:18 -06:00
Ross Thompson
5b4ff4526e
Fixed a bunch of fpga issues.
2021-12-03 17:47:54 -06:00
Ross Thompson
cbb5e4440f
Improved FPGA makefile and fixed timing constraints in clock converter.
2021-12-03 10:05:13 -06:00
Ross Thompson
96fb3acefd
Constraints for fpga are still wrong.
2021-12-02 14:23:21 -06:00
Ross Thompson
303324d370
Added tcl commands to build the implementation.
2021-12-02 10:17:30 -06:00
Ross Thompson
e94fb2aaec
Got fpga synthesis running from scripts.
2021-12-01 16:59:04 -06:00
Ross Thompson
d5f445e0fd
Added make clean to fpga IP generator.
2021-11-29 18:42:28 -06:00
Ross Thompson
a528a86607
Created Makefile to manage IP generation.
2021-11-29 18:33:58 -06:00
Ross Thompson
51807379a8
Added final IP generator script (proc_sys_reset).
2021-11-29 17:43:47 -06:00
Ross Thompson
8aa87958a9
Added ddr4 generator script.
2021-11-29 15:56:57 -06:00
Ross Thompson
da4ed957aa
Created tcl scripts to build 2 of the 4 xilinx IP.
2021-11-29 11:26:08 -06:00
