David Harris
73419f0d41
Added buscachefsm for system with bus and cache
2022-08-25 18:01:01 -07:00
David Harris
d7be94fab2
Cleaned up SelBusWord
2022-08-25 11:18:13 -07:00
David Harris
7a129af9ad
Removed M sufix from busdp signals
2022-08-25 11:13:01 -07:00
David Harris
84ba62a04c
Renamed LSUFunct3M to Funct3 in busdp
2022-08-25 11:08:12 -07:00
David Harris
78618f5fc0
Renaming LSU signals from busdp
2022-08-25 11:05:10 -07:00
David Harris
cd02c894df
renamed BusBuffer to FetchBuffer
2022-08-25 10:44:39 -07:00
David Harris
89860588b8
Renamed AHB signals coming out of LSU to LSH_<AHBNAME>
2022-08-25 09:52:08 -07:00
David Harris
4ecdbb308a
Renamed DCache to Cache in busdp/busfsm signal interface
2022-08-25 06:21:22 -07:00
David Harris
cb2c0fe027
Minor name cleanups
2022-08-25 04:28:25 -07:00
Ross Thompson
ee3d968da0
Found small bug in busfsm which was issuing 1 extra memory read after each cache line fetch. Does not appear to have translated to an extra read out of ahblite.
2022-08-23 18:51:11 -05:00
Ross Thompson
5301444a61
Changed signal names.
2022-08-17 16:12:04 -05:00
Ross Thompson
970a90dd72
Better name for LSUBusWriteCrit. Changed to SelLSUBusWord.
2022-08-17 16:09:20 -05:00
slmnemo
5a6eae214a
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2022-06-09 17:50:47 -07:00
slmnemo
3e8d3bae88
Changes made on 9th Jun
2022-06-09 17:33:51 -07:00
slmnemo
054cf5f7b0
Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors
2022-06-08 15:03:15 -07:00
slmnemo
2d76953d42
Added lock signal to ensure AHB speaks with the right bus
2022-06-08 02:19:21 +00:00
slmnemo
6d36150c3d
Fixed off-by-one error in busdp capture
2022-06-07 19:36:39 +00:00
slmnemo
73e0c1c07f
Reworked bus to handle burst interfacing
2022-06-07 11:22:53 +00:00
slmnemo
847c7930c4
added LSUBurstDone signal to signal when a burst has finished
2022-05-26 16:29:13 -07:00
slmnemo
80fc716cd7
Added signal to monitor HBURST and comments for each burst in busdp
2022-05-26 13:35:49 -07:00
slmnemo
08430a1e85
added burst size signals to the IFU, EBU, LSU, and busdp
2022-05-25 18:02:50 -07:00
Ross Thompson
75e93baaee
Marked signals for name changes.
2022-03-08 17:41:02 -06:00
Ross Thompson
3ec32d7ce8
Removed unused signal.
2022-03-08 16:58:26 -06:00
David Harris
2cea3349ad
LSU/Cache code review notes
2022-03-04 00:07:31 +00:00
Ross Thompson
15f6871a8d
Added generates to pcnextf muxes for privileged and caches.
2022-02-22 22:45:00 -06:00
Ross Thompson
59f04f2518
Minor busdp cleanup.
2022-02-22 17:28:26 -06:00
Ross Thompson
beac362364
Moved a few muxes around after sww changes.
2022-02-16 15:43:03 -06:00
Ross Thompson
6a2bcfcd01
cleanup of signal names.
2022-02-16 15:29:08 -06:00
Ross Thompson
7ffbc6b2ab
Changed names of signals in cache.
2022-02-13 15:06:18 -06:00
Ross Thompson
6d12010d02
Fixed subtle and infrequenct bug.
...
Loading buildroot at 483M instructions started with a spill + ITLBMiss. The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation. However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation. Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.
2022-02-11 10:46:06 -06:00
Ross Thompson
689c32215f
Fixed bugs in ifu spills and missing reset on bus data register.
2022-02-10 18:11:57 -06:00
Ross Thompson
fdb4f909fc
Cleanup + critical path optimizations.
2022-02-10 11:11:16 -06:00
Ross Thompson
ea84211ff9
Removed unused ports from caches and buses.
2022-02-04 22:52:51 -06:00
Ross Thompson
011ad09341
Cleanup.
2022-02-04 22:40:51 -06:00
Ross Thompson
4074f695e0
Moved the hwdata mux back into the busdp.
2022-02-04 22:39:13 -06:00
Ross Thompson
40eb055861
Merged together the two sub cache line read muxes.
...
One mux was used for loads and the other for eviction.
2022-02-04 22:30:04 -06:00
Ross Thompson
290430cda8
Moved the sub cache line read logic to lsu/ifu.
2022-02-04 20:42:53 -06:00
David Harris
a6708ed887
cache cleanup
2022-02-03 15:36:11 +00:00
David Harris
da8819d64b
changed DMEM and IMEM configurations to support BUS/TIM/CACHE
2022-02-03 00:41:09 +00:00
Ross Thompson
4422e2f91c
Repaired wavefile and fixed modelsim warning.
2022-01-31 12:34:17 -06:00
Ross Thompson
f4e62bcb54
Cleanup busdp.
2022-01-31 12:17:07 -06:00
Ross Thompson
9cd502d0af
Encapsulated dtim.
2022-01-31 11:23:55 -06:00
Ross Thompson
c939eb20eb
Removed unused signals in the LSU.
2022-01-31 10:35:35 -06:00
Ross Thompson
a4f6653cd8
Encapsulated the bus data path into a separate module.
2022-01-31 10:15:48 -06:00
