16 Commits

Author	SHA1	Message	Date
Thomas Fleming	4bae666fa1	Implement virtual memory protection	2021-04-21 19:58:36 -04:00
Thomas Fleming	6188f10732	Move InstrPageFault to fetch stage	2021-04-13 13:39:22 -04:00
Thomas Fleming	fdb20ee1cf	Implement sfence.vma and fix tlb writing	2021-04-01 15:55:05 -04:00
Thomas Fleming	e3900bd0fa	Finish finite state machines for page table walker	2021-03-25 02:48:40 -04:00
bbracker	02e924e55a	instrfaults not respecting stalls bugfix	2021-03-25 00:16:26 -04:00
Shreya Sanghai	1d6a2989ed	PC counts branch instructions	2021-03-23 14:25:51 -04:00
Shreya Sanghai	bbe0957df5	Merge branch 'gshare' into main ... Conflicts: wally-pipelined/regression/wave.do	2021-03-18 17:25:48 -04:00
Thomas Fleming	7f7597e667	Connect tlb, pagetablewalker, and memory	2021-03-18 14:35:46 -04:00
Shreya Sanghai	08e9149e20	made performance counters count branch misprediction	2021-03-16 11:24:17 -04:00
Thomas Fleming	7e11317a2d	Export SATP_REGW from csrs to MMU modules	2021-03-05 01:22:53 -05:00
David Harris	cf03afa880	Eliminated flushing pipeline on CSR reads	2021-02-26 17:00:07 -05:00
David Harris	37dba8fd26	More memory interface, ALU testgen	2021-02-15 10:10:50 -05:00
David Harris	d56d7a75a6	Rename ifu/dmem/ebu signals to match uarch diagram	2021-02-02 15:09:24 -05:00
David Harris	aad1d3d7dd	Moved writeback pipeline registers from datapth into DMEM and CSR	2021-02-02 13:02:31 -05:00
David Harris	9d7e242596	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
David Harris	396cea1ea7	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00