Ross Thompson
86de36b6ce
FPGA makefile update.
2023-04-25 16:24:26 -05:00
Ross Thompson
d513956bb9
Updated fpga Makefile to work with both the Arty and VCU platforms.
2023-04-21 11:08:35 -05:00
Ross Thompson
5da5b76449
Fixed more issues with arty a7 constarints.
2023-04-16 13:25:02 -05:00
Ross Thompson
679dc7d73b
Progress on arty a7 board.
2023-04-13 17:57:12 -05:00
Ross Thompson
b015e736a0
Updated to help debut Jacob's crossbar woes.
2023-04-11 14:22:42 -05:00
Ross Thompson
d2d528cf3c
Finally building ddr3 xilinx ip from script.
2023-04-10 14:36:33 -05:00
David Harris
99d179dd3e
Removed pipelined level of hierarchy
2023-02-02 14:14:11 -08:00
Ross Thompson
442de3f5b7
Updated fpga constraints.
2023-01-20 20:16:33 -06:00
Ross Thompson
b709c224ab
Updated ignore to exclude copied files.
2023-01-20 19:47:33 -06:00
Ross Thompson
e06237ad92
Removed mark_debug vivado directive from source code.
...
Created script to add mark_debug directive to source code based on a file which contains locations and signal which need them for the FPGA debugger.
Files output to temporary directory.
2023-01-20 19:43:18 -06:00
Ross Thompson
3e1a54e80a
Removed SDC from repo due to copy right issue.
...
Modified fpga build flow to reference it outside the repo.
2023-01-20 14:57:06 -06:00
Ross Thompson
b7224cc5ba
Updated fpga constraints.
2022-12-21 14:50:01 -06:00
Ross Thompson
fd1ef82310
Fixed bug with fpga makefile.
2022-11-07 09:20:05 -06:00
Ross Thompson
1510c2d92f
Setup to run with both the vcu108 and vcu118 boards. Set the parameters in the Makefile.
2022-10-24 15:38:39 -05:00
Ross Thompson
68745d40f2
Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language.
2021-12-12 17:21:44 -06:00
Ross Thompson
cbb5e4440f
Improved FPGA makefile and fixed timing constraints in clock converter.
2021-12-03 10:05:13 -06:00
Ross Thompson
d5f445e0fd
Added make clean to fpga IP generator.
2021-11-29 18:42:28 -06:00
Ross Thompson
a528a86607
Created Makefile to manage IP generation.
2021-11-29 18:33:58 -06:00
