Ross Thompson
460b37b21a
Added additional suppresses to vsim command incase buildroot files are missing.
2022-02-16 17:05:54 -06:00
Skylar Litz
03f23d2aaa
update bugfinder script to new file organization
2022-02-15 22:58:18 +00:00
Ross Thompson
1d7949513d
More cache cleanup.
2022-02-13 15:47:27 -06:00
Ross Thompson
7ffbc6b2ab
Changed names of signals in cache.
2022-02-13 15:06:18 -06:00
Ross Thompson
33beaa4593
Updates to linux wave.
2022-02-11 13:28:18 -06:00
Ross Thompson
d9f77d3659
Updated linux wave.
2022-02-11 13:15:42 -06:00
Ross Thompson
1a1629c62f
linux wave cleanup.
2022-02-11 10:48:45 -06:00
Ross Thompson
6d12010d02
Fixed subtle and infrequenct bug.
...
Loading buildroot at 483M instructions started with a spill + ITLBMiss. The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation. However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation. Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.
2022-02-11 10:46:06 -06:00
Ross Thompson
9fb612d4ff
Updated wave files to reflect recent changes.
2022-02-10 17:52:19 -06:00
Ross Thompson
4fd0154d03
Added commented out commands to generate saif file from vsim.
2022-02-09 18:40:45 -06:00
David Harris
c61cd55c5c
Merged TIM and regular testbenches. RV32e now working and back in regression.
2022-02-08 12:18:13 +00:00
David Harris
cbef88ec10
Lab 3 file cleanup
2022-02-08 10:26:37 +00:00
David Harris
50b44b4416
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-07 14:43:31 +00:00
David Harris
9b55848ffc
Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration
2022-02-06 01:22:40 +00:00
bbracker
74ef58e20e
remove rv32e from regression because it is broken; goes with previous commit
2022-02-05 23:05:21 +00:00
David Harris
0f7b8017d1
Modified regression to use proper rv32e test name, but rv32e_wally32e still isn't passing due to loop exceeding iteration limit
2022-02-05 05:35:51 +00:00
David Harris
a9d2386010
Merged buildroot do files into wally-pipelined do files, added work suffixes so buildroot regression won't fail due to file conflicts
2022-02-05 05:28:40 +00:00
David Harris
66b4834ef5
Modified wally-pipelined-batch.do to handle buildroot
2022-02-05 05:07:07 +00:00
David Harris
72bc64ef28
Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.
2022-02-05 04:16:18 +00:00
David Harris
2c67f32b97
RV32e tests
2022-02-04 14:30:36 +00:00
David Harris
ef5af9b5fd
renamed configs
2022-02-03 23:36:41 +00:00
David Harris
a6708ed887
cache cleanup
2022-02-03 15:36:11 +00:00
Ross Thompson
b642a19e12
Merge branch 'makefiles' into main
2022-02-03 08:33:50 -06:00
Ross Thompson
c34907c95b
Completed makefile updates to accelerate the generation of memfiles. There are two makefiles in the
...
regression directory. Makefile calls the submakefiles for generating elf files.
The second makefile-memfiles generates the memfiles, addr, and label files.
2022-02-03 08:32:48 -06:00
Ross Thompson
9336682749
Manged to get all the tests compiled and converted to memfiles using new makefiles.
2022-02-03 00:00:15 -06:00
Ross Thompson
06c5a825c4
Quick patch to regression-wally to "fix" rv32ic.
2022-02-02 19:24:24 -06:00
Ross Thompson
5c640b6582
broken makefiles.
2022-02-02 19:15:11 -06:00
Ross Thompson
943dff106e
Broken makefiles.
2022-02-02 19:14:42 -06:00
David Harris
38bbe23d14
More config file cleanup; 32ic tests broken
2022-02-03 01:08:34 +00:00
Ross Thompson
98990a294c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-02 11:41:54 -06:00
David Harris
4ba37d5cc0
Config file & wally-riscv-arch-test cleanup
2022-02-02 16:35:52 +00:00
Ross Thompson
2d827bf8c0
Added helpful signals to wavefile.
...
Makefile for tests now creates the function address to name mapping files.
The function name and test name are included in the wave file.
2022-02-02 10:15:54 -06:00
Ross Thompson
143bdaa288
Modified makefiles to generate function address to name mappings for modelsim.
2022-02-01 18:25:03 -06:00
Ross Thompson
f055441ecf
Improved function_radix to not printout warnings when no valid function is found.
2022-02-01 18:03:09 -06:00
Ross Thompson
5407b72af9
Setup the main regression test to be able to handle coremark.
2022-02-01 17:00:11 -06:00
Ross Thompson
c9a163b8fd
Repaired linux-wave.do
2022-01-31 12:54:18 -06:00
Ross Thompson
4422e2f91c
Repaired wavefile and fixed modelsim warning.
2022-01-31 12:34:17 -06:00
Ross Thompson
2e00186eea
Updated wave.do to match the ifu/lsu changes.
2022-01-28 14:37:15 -06:00
Ross Thompson
862bf2faae
Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
2022-01-27 17:11:27 -06:00
Ross Thompson
284d671da3
Increased number of concurrent tests.
2022-01-27 08:45:25 -06:00
Ross Thompson
3ebcd35a8c
Added colors to regression script to make it easy to pick out success from fail.
2022-01-26 22:40:32 -06:00
Ross Thompson
42ef1e22e5
1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.
...
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
2022-01-26 18:23:39 -06:00
David Harris
39d318fb2a
Fixed path to riscvOVPsimPlus
2022-01-21 00:12:14 +00:00
David Harris
07425369fc
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
David Harris
cea09aab98
Removed imperas tests from makefile for now
2022-01-20 14:51:56 +00:00
David Harris
fc932ef0ff
Added top-level make clean
2022-01-20 14:17:26 +00:00
David Harris
ebf9f5d526
riscvsingle reparittioned to match Ch4
2022-01-17 16:57:32 +00:00
David Harris
55b4423329
Added E extension, and downloaded riscv-dv and embench-iot to addins
2022-01-17 14:42:59 +00:00
David Harris
325724f556
LSU Cleanup
2022-01-15 01:11:17 +00:00
David Harris
6febce0001
Moved Dcache into bus block
2022-01-15 00:39:07 +00:00
