Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity
5,063 Commits 14 Branches 1 Tag 31 MiB
4550966678
Commit Graph

2046 Commits

Author SHA1 Message Date
Ross Thompson
4550966678 More btb cleanup. 2023-01-25 12:14:18 -06:00
Ross Thompson
40b4811d2b Found minor bug in gshare. 2023-01-25 12:08:54 -06:00
Ross Thompson
afdcfeb93b BTB cleanup. 2023-01-25 12:05:13 -06:00
Ross Thompson
7e1363bfad Optomized gshare. 2023-01-25 11:41:16 -06:00
Ross Thompson
b931110f2d Renamed file missed from last commit. 2023-01-25 10:17:43 -06:00
Ross Thompson
ad6f7041b4 Fixed wrong header on optgshare.sv. Somehow it still had the old MIT license. 
Renamed ram2p1rwbefix.sv to ram2p1rwbe.sv
 2023-01-25 10:14:30 -06:00
Ross Thompson
56369f7641 Removed old versions of gshare. 2023-01-24 17:26:54 -06:00
Ross Thompson
1acbdaeca6 Removed the old two port ram and replaced it with the fixed version. 
The fixed version is renamed to ram2p1r1wb.sv
 2023-01-24 17:25:16 -06:00
Ross Thompson
1170dc7250 Moved and ranamed btb to btb.sv 
Fixed btb to use the fixed port 2 sram.
 2023-01-24 17:19:51 -06:00
Ross Thompson
7d1109fc24 Partial BTB cleanup. 2023-01-24 16:12:35 -06:00
Ross Thompson
2157970adf Moved branch predictor files into separate sub-directory. 2023-01-24 16:00:27 -06:00
Ross Thompson
5494ee2159 Moved ebufsmarb into its own module. 2023-01-23 23:10:10 -06:00
Ross Thompson
a4d5ccc4d6 Added comments about needing move ebufsm into a new module. 2023-01-23 22:03:49 -06:00
Ross Thompson
1439ff02c7 Added comments to lrsc module. 2023-01-23 17:49:47 -06:00
Ross Thompson
e9f435bbda Oups fixed bug from the last commit. 2023-01-23 17:38:30 -06:00
Ross Thompson
af6899472d Another round of cleanup in the LSU. 2023-01-23 17:27:39 -06:00
David Harris
fc6cf1f198 formatting 2023-01-23 10:54:06 -08:00
David Harris
2d7f39672a Repo cleanup 2023-01-23 10:37:33 -08:00
Ross Thompson
626bcd8608 Removed mark_debug from all source code. 2023-01-20 18:47:36 -06:00
David Harris
45218863af test 2023-01-20 15:23:38 -08:00
David Harris
3d13683c07 Continued framework for B instructions 2023-01-20 14:27:13 -08:00
David Harris
a968ae2f66 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-20 14:19:10 -08:00
David Harris
e87c2b2724 Started adding bit manipulation unit 2023-01-20 14:19:07 -08:00
Ross Thompson
0123776037 Updated figure cache references. 2023-01-20 15:01:54 -06:00
Ross Thompson
3e1a54e80a Removed SDC from repo due to copy right issue. 
Modified fpga build flow to reference it outside the repo.
 2023-01-20 14:57:06 -06:00
Ross Thompson
2e9b5f9ae4 Formatting. 2023-01-20 13:13:05 -06:00
Ross Thompson
bcadbd7104 Formatting. 2023-01-20 13:09:42 -06:00
Ross Thompson
ecceea177a Formatting. 2023-01-20 13:05:10 -06:00
Ross Thompson
3d202ed2fd Reformatting cachefsm. 2023-01-20 12:49:55 -06:00
Ross Thompson
d3df8e062e Formatting. 2023-01-20 12:41:57 -06:00
Ross Thompson
1ecf4e4cc9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-20 12:37:12 -06:00
Ross Thompson
74ab386735 More cleanup and formatting. 2023-01-20 12:34:40 -06:00
David Harris
26cb45e240 renamed comparator module 2023-01-20 10:13:47 -08:00
Ross Thompson
340e1797ea More cleanup and formatting. 2023-01-20 12:09:21 -06:00
Ross Thompson
c5169a3e39 Formatting. 2023-01-20 11:51:10 -06:00
Ross Thompson
5b5a615e4a Integrated the missing zifence tests into the regression test. 2023-01-20 10:34:49 -06:00
Ross Thompson
29f45d6203 Imperas found a bug with the Fence.I instruction. 
If a fence.i directly followed a store miss, the d$ would release Stall during the cache line write.
Then transition to ReadHold.  This cause the d$ flush to go high while in ReadHold.  The solution is
to ensure the cache continues to assert Stall while in WriteLine state.

There was a second issue also.  The D$ flush asserted FlushD which flushed the I$ invalidate.
Finally the third issue was CacheEn from the FSM needs to be asserted on an InvalidateCache.
 2023-01-20 10:17:21 -06:00
Ross Thompson
da4eec7e0e Improved comment. 2023-01-19 17:41:57 -06:00
Ross Thompson
117ff8163b ram uses always rather than always_ff due to modelsim issue. 2023-01-19 17:41:15 -06:00
Ross Thompson
23ab178192 Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2023-01-19 17:28:53 -06:00
Ross Thompson
928e06d4fa Added comment about needed changes in BTB. 2023-01-19 17:28:00 -06:00
David Harris
569a016efa Removed study versions from comparator 2023-01-19 15:13:35 -08:00
David Harris
0488723db9 Moved unused study files to studies directory 2023-01-19 15:13:11 -08:00
David Harris
9df5fdbd89 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-19 14:47:54 -08:00
David Harris
25b607566c RAM declaration cleanup: 2023-01-19 14:47:51 -08:00
Ross Thompson
b027921902 Formatting. 2023-01-19 15:06:37 -06:00
Ross Thompson
ea96c2375f Formatting. 2023-01-19 14:18:46 -06:00
Ross Thompson
e380fd71ff Formatting and name changes. 2023-01-19 14:16:29 -06:00
Ross Thompson
47fdff6488 Formatting. 2023-01-18 19:26:20 -06:00
Ross Thompson
49daa736b1 Formatting spillsupport. 2023-01-18 19:25:54 -06:00