Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity
3,238 Commits 14 Branches 1 Tag 31 MiB
42eb771521
Commit Graph

3238 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Kip Macsai-Goren
42eb771521 comment cleanup 2022-04-25 17:47:10 +00:00
Shreya Sanghai
975005dbfa automate synth 2022-04-25 16:03:32 +00:00
bbracker
ce56e2dd73 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-25 08:01:39 -07:00
David Harris
0957b7040d Restored MPRV behavior per spec 2022-04-25 14:52:18 +00:00
David Harris
1a8369b02b Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields 2022-04-25 14:49:00 +00:00
bbracker
6f63b88c60 upgrade Buildroot Makefile to also copy over vmlinux 2022-04-25 07:36:59 -07:00
David Harris
142636173e Added MTINST hardwired to 0, and added timeout of U-mode WFI 2022-04-24 20:00:02 +00:00
David Harris
28e8aa4f97 Fixed InstrMisalignedFaultM mtval 2022-04-24 17:31:30 +00:00
David Harris
ffecdda6e6 Improved priority order and mtval of traps to match spec 2022-04-24 17:24:45 +00:00
David Harris
04b0579b89 Extended sim time to fully boot Linux. Added comments to hazard unit 2022-04-24 13:51:00 +00:00
Kip Macsai-Goren
08d4c29724 Removed test cases irrelevant to this implementation, added explanatory comments. 2022-04-22 23:06:52 +00:00
Kip Macsai-Goren
abfbbaccba Added testing for every bit field in MIE, rather than just one 2022-04-22 23:05:54 +00:00
Kip Macsai-Goren
7630a0be42 fixed timeouts on GPIO test by enabling pins as inputs as well as outputs. 2022-04-22 22:46:11 +00:00
Kip Macsai-Goren
bd87af478a Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address) 2022-04-22 22:46:11 +00:00
bbracker
cd70175e5a less hardcoded paths in Makefile 2022-04-21 20:42:02 -07:00
bbracker
9eec1a83a6 deprecate unused LINUX_FIX_READ macro 2022-04-21 19:14:47 -07:00
bbracker
9c1e398bb5 change how tristate I/O is spoofed in GPIO loopback test 2022-04-21 10:31:16 -07:00
Ross Thompson
e56b9f18d5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-21 09:52:42 -05:00
Ross Thompson
a86274a1e0 Modified wally-pipelined.do for no trace linux sim. 2022-04-21 09:52:33 -05:00
David Harris
6793533676 Removed FP vectors Readme 2022-04-21 04:55:27 +00:00
David Harris
1e19cf9f14 Simplified profile for UART boot; added warnings on UART Rx errors 2022-04-21 04:54:45 +00:00
Kip Macsai-Goren
25d0f6305a added new tests to tests.vh 2022-04-20 17:34:40 +00:00
Kip Macsai-Goren
53f6b5fada added 32 bit tests to makefrag 2022-04-20 17:33:56 +00:00
Kip Macsai-Goren
0a6e1d108f updated 32 bit test lib to mirror 64 bit one in interrupt handling, trap stacks 2022-04-20 17:33:40 +00:00
Kip Macsai-Goren
fe14b9f188 Added 32 bit privilege tests that work but for one bug 2022-04-20 17:32:29 +00:00
Kip Macsai-Goren
8e72ace5ac fixed rv32ia to support clint and GPIO for priv tests 2022-04-20 17:31:34 +00:00
Kip Macsai-Goren
7ed0c7b8b6 Updated 32 bit PMA tests to reflect new clint rules 2022-04-20 17:31:08 +00:00
Kip Macsai-Goren
5f78999424 added some explanatory comments 2022-04-20 06:48:01 +00:00
Kip Macsai-Goren
5cb5ba0c8c Added interrupt time loop support, fixed external interrupts, fixed delegated ecallhandler 2022-04-20 06:48:01 +00:00
Kip Macsai-Goren
324d3fcea5 added working general trap tests to regression 2022-04-20 06:48:01 +00:00
Ross Thompson
b94927d8a6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-19 14:09:50 -05:00
David Harris
c57b9e6703 Added baby torture tests 2022-04-19 15:13:06 +00:00
David Harris
eaa0d44980 Fixed WFI decoding in IFU 2022-04-18 19:02:08 +00:00
David Harris
b4028899fe Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-04-18 17:59:56 +00:00
David Harris
ba578b21d8 Removed extra fields from fp vectors 2022-04-18 17:59:48 +00:00
Kip Macsai-Goren
ced763beb6 Added GPIO loopback to let outputs cause interrupts 2022-04-18 07:22:49 +00:00
Kip Macsai-Goren
121cc627f6 Added working trap test to regression, fixed hanfling of some interrupts 2022-04-18 07:22:16 +00:00
Shreya Sanghai
1f229c5387 automate synth 2022-04-18 04:21:03 +00:00
Shreya Sanghai
9538338d8e added frequency configs for makefile 2022-04-18 04:21:03 +00:00
Shreya Sanghai
6f0085201b replaced k with bpred size 2022-04-18 04:21:03 +00:00
Shreya Sanghai
a8b3cc8cf9 added bpred size to wally config 2022-04-18 04:21:03 +00:00
David Harris
22842816a8 LSU name cleanup 2022-04-18 03:18:38 +00:00
Ross Thompson
61dbf13a69 Fixed bug I introduced by csrc cleanup and changes to ILA. 2022-04-17 21:45:46 -05:00
David Harris
e04febdb57 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-04-18 01:30:11 +00:00
David Harris
c07b9d1722 Renamed FinalAMOWriteDataM to AMOWriteDataM 2022-04-18 01:30:03 +00:00
David Harris
6504017044 Run 4M instructions in buildroot test to get through kernel & VirtMem startup 2022-04-18 01:29:38 +00:00
Ross Thompson
a5d4e39e7d Added back the instret counter to ILA. 2022-04-17 18:44:07 -05:00
Ross Thompson
0bcfd9d666 Added another GPR to debugger. 2022-04-17 18:12:05 -05:00
Ross Thompson
3add26be64 fixed no forcing bug in linux testbench. 2022-04-17 17:49:51 -05:00
David Harris
d8b4c985cd Remvoed bytemask anding from FinalWriteDataM in subwordwrite 2022-04-17 22:33:25 +00:00