David Harris
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3e8026dc21
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Configurable number of performance counters
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2021-06-10 09:41:26 -04:00 |
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David Harris
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75870a16d7
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Restored PCCorrectE declaration in IFU
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2021-06-09 21:09:16 -04:00 |
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David Harris
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a2c054d0d2
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-06-09 21:03:16 -04:00 |
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David Harris
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0ffbd03139
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More verilator fixes, but bpred is broken
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2021-06-09 21:03:03 -04:00 |
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David Harris
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c7e57aeb1a
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removed verilator lint_off WIDTH
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2021-06-09 21:01:44 -04:00 |
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David Harris
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01d6ca1e2a
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Fixed lint WIDTH errors
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2021-06-09 20:58:20 -04:00 |
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bbracker
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75257f2ab2
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-06-09 15:14:49 -04:00 |
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bbracker
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449ac22ecf
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log only half of bootmem for memory map convenience -- works ok for now because bootmem is half empty
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2021-06-09 15:14:42 -04:00 |
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David Harris
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2952550db7
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More PMP entries
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2021-06-08 15:33:06 -04:00 |
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David Harris
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90e5781471
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Start to parameterize number of PMP Entries
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2021-06-08 15:29:22 -04:00 |
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Kip Macsai-Goren
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a95a7a7b82
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working version with new mmu comments, old boottim values
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2021-06-08 15:20:25 -04:00 |
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Kip Macsai-Goren
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2155cb2e91
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merge of reverted main into up to date main
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2021-06-08 14:57:43 -04:00 |
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Kip Macsai-Goren
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361c71c5e9
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reverted to working version with new mmu comments
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2021-06-08 14:56:00 -04:00 |
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David Harris
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b613f46c2d
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Resized BOOT TIM to 1 KB
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2021-06-08 14:04:32 -04:00 |
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Kip Macsai-Goren
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aab7bd94f7
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Merge small mmu changes into main
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2021-06-08 14:00:26 -04:00 |
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Kip Macsai-Goren
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d6f47d5917
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making mmu branch line up with main
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2021-06-08 13:59:03 -04:00 |
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Kip Macsai-Goren
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e209dbcf50
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some cleanup of signals, not done yet
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2021-06-08 13:39:32 -04:00 |
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bbracker
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cc91c774a6
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Ah big ole merge! Passes sim-wally-batch and linting, so should be fine
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2021-06-08 12:41:25 -04:00 |
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bbracker
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e7e4105931
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* GPIO comprehensive testing
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
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2021-06-08 12:32:46 -04:00 |
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Kip Macsai-Goren
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49515245d9
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remove redundant decodes, fixed mmu logic ins/outs
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2021-06-07 19:23:30 -04:00 |
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Kip Macsai-Goren
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1e174a8244
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got rid of some underscores in filenames, modules
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2021-06-07 18:54:05 -04:00 |
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Kip Macsai-Goren
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c96695b1b6
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implemented simpler page mixers, cleaned up a bit
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2021-06-07 18:32:34 -04:00 |
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Kip Macsai-Goren
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b27abc53e8
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began updating cam line to reduce muxes, confusion
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2021-06-07 17:03:31 -04:00 |
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Kip Macsai-Goren
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6a63ad04d2
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regression working partially done page mask
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2021-06-07 17:02:31 -04:00 |
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David Harris
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9efbffdee5
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-06-07 16:14:13 -04:00 |
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David Harris
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43a690dc42
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Simplified superpage matching
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2021-06-07 16:11:28 -04:00 |
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Katherine Parry
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0acf665a8b
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lint is clean
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2021-06-07 14:22:54 -04:00 |
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bbracker
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28c6d60150
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temporarily removing buildroot from regression until it is regenerated
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2021-06-07 13:20:50 -04:00 |
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David Harris
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2ae5ca19b5
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Continued merge
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2021-06-07 12:49:47 -04:00 |
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David Harris
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ff62000e2c
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Second attept to commit refactoring config files
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2021-06-07 12:37:46 -04:00 |
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David Harris
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dc0b19dfaa
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Merge difficulties
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2021-06-07 09:50:23 -04:00 |
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David Harris
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d5ec797ba4
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Refactored configuration files and renamed testbench-busybear to testbench-linux
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2021-06-07 09:46:52 -04:00 |
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Katherine Parry
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75a6097467
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fixed lint warnings for fpu and lzd
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2021-06-05 12:06:33 -04:00 |
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Kip Macsai-Goren
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49200bd922
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Cleaned up some unused signals
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2021-06-04 21:04:19 -04:00 |
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Kip Macsai-Goren
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22e8e06ac7
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moved privilege dfinitions into wally-constants, upgraded relevant includes
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2021-06-04 17:55:07 -04:00 |
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Kip Macsai-Goren
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037aa6fa89
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Merge branch 'mmu' into main
new mmu unit and moving pmp/pma now passes regression except for lint and buildroot
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2021-06-04 17:07:56 -04:00 |
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Kip Macsai-Goren
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3493027bf5
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added shared constants file list of includes
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2021-06-04 17:05:47 -04:00 |
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Kip Macsai-Goren
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1ae529c450
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restructured so that pma/pmp are a part of mmu
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2021-06-04 17:05:07 -04:00 |
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Ross Thompson
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41a1e6112a
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-06-04 15:16:39 -05:00 |
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Ross Thompson
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7406e33b61
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Continued I-Cache cleanup.
Removed strange mux on InstrRawD along with
the select logic.
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2021-06-04 15:14:05 -05:00 |
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Ross Thompson
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191f7e61fd
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Moved I-Cache offset selection mux to icache.sv (top level).
When we switch to set associative this is will be more efficient.
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2021-06-04 13:49:33 -05:00 |
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Ross Thompson
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e0d0fdd708
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Cleaned up the I-Cache memory.
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2021-06-04 13:36:06 -05:00 |
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Katherine Parry
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fc65aedbd6
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Double-precision FMA instructions
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2021-06-04 14:00:11 -04:00 |
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Ross Thompson
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fdef8df76b
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Reorganized the icache names.
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2021-06-04 12:53:42 -05:00 |
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Ross Thompson
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7c44f19925
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Relocated the icache to the cache directoy.
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2021-06-04 12:23:46 -05:00 |
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Ross Thompson
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21b1145bdf
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Added special tests for checking the accuracy of global and gshare branch
predictors.
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2021-06-04 11:01:54 -05:00 |
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David Harris
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a26bf37be8
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Started MMU
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2021-06-04 11:59:14 -04:00 |
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Ross Thompson
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f55af8eb1f
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updated isa extensions for simple branch predictor test.
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2021-06-04 10:41:32 -05:00 |
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David Harris
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4f71964529
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Fixed RV32 MMU constants
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2021-06-04 09:15:42 -04:00 |
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David Harris
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0674f5506e
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moved shared constants to a shared directory
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2021-06-03 22:41:30 -04:00 |
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