15 Commits

Author	SHA1	Message	Date
David Harris	f5e9c91193	All tests passing with bus interface	2021-02-24 07:25:03 -05:00
David Harris	c52a99ce2d	Fixed fetch stall after jump in bus unit	2021-02-23 09:08:57 -05:00
David Harris	817f81c356	Debugging Bus interface	2021-02-22 13:48:30 -05:00
David Harris	183a2dcfb5	Debugging bus interface.	2021-02-10 01:43:54 -05:00
David Harris	2357f5513b	Debugging instruction fetch	2021-02-09 11:02:17 -05:00
David Harris	3551cc859b	Data memory bus integration	2021-02-07 23:21:55 -05:00
David Harris	396cea1ea7	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00
David Harris	9c81278f28	Added HCLK and HRESETn	2021-01-30 00:56:12 -05:00
David Harris	a357f2a0e7	Connected AHB bus to Uncore	2021-01-29 23:43:48 -05:00
David Harris	dc2443c55b	Moving data memory to uncore	2021-01-29 15:37:51 -05:00
David Harris	ed3cb83c10	Added ahblite bus interface unit	2021-01-29 01:07:17 -05:00
David Harris	824014c5c0	Repartitioned with Instruction Fetch Unit, Integer Execution Unit	2021-01-27 22:49:47 -05:00
David Harris	616afaba69	Moved privileged unit from datapath to hart	2021-01-27 07:46:52 -05:00
David Harris	b88508ca11	Repartitioned datapath and controller into ieu	2021-01-27 06:40:26 -05:00
David Harris	fa18052348	Added test configurations	2021-01-25 11:28:43 -05:00