Katherine Parry
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3476579e02
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-08 12:30:50 -07:00 |
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Katherine Parry
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9ef45f36fd
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renamed signals in cvt and prostproc
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2022-07-08 12:30:43 -07:00 |
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James Stine
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c5dfefe669
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Update SRAM to /proj/wally
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2022-07-08 08:09:55 -05:00 |
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David Harris
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d10ad0e883
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Removed testbench code that ignores mismatch on zero signatures
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2022-07-08 09:17:31 +00:00 |
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David Harris
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c72e4d43d2
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erge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-08 09:09:07 +00:00 |
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David Harris
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381f3298d8
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Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc
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2022-07-08 09:09:02 +00:00 |
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David Harris
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1ce0975366
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Adjusting byte writes to RAM
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2022-07-08 08:45:21 +00:00 |
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David Harris
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3f9e662201
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Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables
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2022-07-08 08:44:37 +00:00 |
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David Harris
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9b6d9666c5
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Removed unused swbytemask from CLINT
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2022-07-08 08:43:24 +00:00 |
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Katherine Parry
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905b7ffc84
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moved unsused division code again
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2022-07-07 16:41:26 -07:00 |
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cturek
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b7e590ebb0
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Sqrt exponents
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2022-07-07 23:34:56 +00:00 |
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Katherine Parry
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5751d86f69
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-07 16:29:44 -07:00 |
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Katherine Parry
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2bbde827e6
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Revert "moved old divsqrt to unusedsrc"
This reverts commit c9f5ae12ea.
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2022-07-07 16:29:17 -07:00 |
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DTowersM
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5a68ff9afb
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD
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2022-07-07 23:11:35 +00:00 |
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DTowersM
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d55833e4f3
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new slim benchmarks/coremark directory now works on addins/coremark repo, removed old riscv-coremark directory
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2022-07-07 23:11:02 +00:00 |
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Katherine Parry
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c9f5ae12ea
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moved old divsqrt to unusedsrc
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2022-07-07 16:09:56 -07:00 |
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Katherine Parry
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41c16be012
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srt divider merged into fpu
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2022-07-07 16:01:33 -07:00 |
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cturek
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b41a6f069b
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Seventeen Square Root Tests
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2022-07-07 22:48:46 +00:00 |
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David Harris
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96a75d7749
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-07 22:00:59 +00:00 |
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Katherine Parry
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08769e35ae
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modified wally shared
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2022-07-07 21:59:43 +00:00 |
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David Harris
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2f342c430e
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fixing port errors
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2022-07-07 21:57:10 +00:00 |
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Katherine Parry
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0b40f38f02
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added load and store test
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2022-07-07 21:48:51 +00:00 |
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cturek
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89e17b6f3c
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Preprocessing for square root
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2022-07-07 21:23:30 +00:00 |
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David Harris
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88e3233935
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Preliminary SRAM integration
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2022-07-07 19:56:20 +00:00 |
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David Harris
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b7462ed6ed
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-07 15:51:33 +00:00 |
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slmnemo
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c5fd98ba99
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sim-buildroot-batch now runs wally-pipelined-batch
with option buildroot buildroot-no-trace to boot linux from step 0
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2022-07-06 18:06:43 -07:00 |
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David Harris
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6a030fc2a3
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-06 23:44:47 +00:00 |
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DTowersM
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47a990d9f1
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into HEAD
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2022-07-06 23:44:27 +00:00 |
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DTowersM
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1e8ccf3449
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added changes to the testbench and benchmarks/coremark to support running the addins directory without the fpu
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2022-07-06 23:43:57 +00:00 |
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David Harris
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08ae2db080
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-06 23:43:05 +00:00 |
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Ross Thompson
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bd46cf76a9
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Fixed an issue with direct map cache's nextway logic.
Also found a small error in the replacement policy.
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2022-07-06 18:34:30 -05:00 |
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Madeleine Masser-Frye
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cb33d2289b
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fixed width mismatch for rv64 ieuadrM and readdatawordM
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2022-07-06 22:39:35 +00:00 |
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David Harris
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9ef38145d7
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-06 13:26:26 +00:00 |
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David Harris
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a599084b88
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PLIC and UART passing tests on APB
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2022-07-06 13:26:14 +00:00 |
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Madeleine Masser-Frye
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846f12aa2e
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new priority onehot module for better area/time
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2022-07-06 00:08:59 +00:00 |
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Madeleine Masser-Frye
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01e6d69a67
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took first match out of pmpadrdec
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2022-07-06 00:02:01 +00:00 |
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Madeleine Masser-Frye
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50e9b6ac53
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fixed concatenation syntax
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2022-07-05 22:36:54 +00:00 |
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cturek
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e7ac99a683
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Radix 2 Integer division working (without signs or remainder)
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2022-07-05 21:34:49 +00:00 |
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David Harris
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d73645944f
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APB CLINT passing regression
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2022-07-05 15:51:35 +00:00 |
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David Harris
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d033659beb
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Modified uncore to use AHB bridge to GPIO
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2022-07-05 05:02:21 +00:00 |
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David Harris
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e7fe7ad0c8
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AHB bridge for gpio
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2022-07-05 05:01:59 +00:00 |
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David Harris
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4723ff559c
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Added reference to Schmookler01 for LOA
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2022-07-05 05:01:12 +00:00 |
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David Harris
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aa3dc8bfe1
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Added comments to PLIC about likely bug
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2022-07-05 05:00:29 +00:00 |
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David Harris
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4c48d71e4b
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removed delay in ahblite
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2022-07-05 04:59:28 +00:00 |
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David Harris
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dab87811e9
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Removed sig4 spurious message from testbench
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2022-07-05 03:27:14 +00:00 |
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David Harris
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2b3038edf8
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Added check to halt testbench on failing to find file
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2022-07-05 02:28:59 +00:00 |
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Katherine Parry
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010a05f583
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added missing files
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2022-07-03 21:40:47 -07:00 |
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Katherine Parry
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1b4584e825
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Renaming signals to match chapter
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2022-07-03 12:26:22 -07:00 |
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David Harris
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bde1c5eb1b
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-02 19:37:14 +00:00 |
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David Harris
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52dbc9f8be
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FMA ZAligned name
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2022-07-02 19:35:13 +00:00 |
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