bbracker
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3465d8cd32
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improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS
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2022-04-13 03:37:53 -07:00 |
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bbracker
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67ef47b25b
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whoops forgot to update AttemptedInstructionCount in interrupt spoofing
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2022-04-13 00:49:37 -07:00 |
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bbracker
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6c3d274970
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change testbench-linux to by default use attempted instruction count for warning/error messages
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2022-04-12 21:22:08 -07:00 |
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Ross Thompson
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56bea58a3c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-10 13:41:27 -05:00 |
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Ross Thompson
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fc5eac6820
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Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing.
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2022-04-10 13:27:54 -05:00 |
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bbracker
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c0c5733a1d
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upgrade testbench interrupt forcing such that first m_timer interrupt now successfully spoofs
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2022-04-08 13:45:27 -07:00 |
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bbracker
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23406d0926
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small signs of life on new interrupt spoofing
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2022-04-08 12:32:30 -07:00 |
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bbracker
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69a0f6e00b
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big interrupts refactor
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2022-03-30 13:22:41 -07:00 |
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Ross Thompson
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e4f4e1bd43
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-30 11:09:44 -05:00 |
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Ross Thompson
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997c1b87fe
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rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory.
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2022-03-29 23:48:19 -05:00 |
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Skylar Litz
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f91fb7a388
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add AtemptedInstructionCount signal
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2022-03-26 21:28:57 +00:00 |
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bbracker
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6f6663cd67
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fix multiple-context PLIC checkpoint generation
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2022-03-25 01:02:22 +00:00 |
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bbracker
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d33de3ef6b
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tabs vs spaces disagreement
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2022-03-24 17:11:41 -07:00 |
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bbracker
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4b376e2834
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1st attempt at multiple channel PLIC
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2022-03-24 17:08:10 -07:00 |
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Ross Thompson
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71aad2d213
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Moved WriteDataM register into LSU.
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2022-03-23 14:17:59 -05:00 |
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Ross Thompson
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aa60b57fb3
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Cleanup in testbench-linux.sv.
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2022-03-22 22:34:38 -05:00 |
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Ross Thompson
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4ca9458534
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added SIP, SIE, and SSTATUS to checkpoints. Can't seem to get the linux testbench to force SIP.
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2022-03-22 21:28:34 -05:00 |
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Ross Thompson
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e6b42cb10f
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Added spoof of uart addresses +0x2 and +0x6.
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2022-03-22 16:52:27 -05:00 |
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bbracker
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742e8d98cd
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fix up PLIC and UART checkpointing
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2022-03-07 23:48:47 -08:00 |
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bbracker
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92e1583db5
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change testbench-linux.sv to use new shared location of disassembly files
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2022-03-07 20:04:08 -08:00 |
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bbracker
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b6031bb15f
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fix buildroot checkpointing and add it back to regression
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2022-03-02 16:00:19 +00:00 |
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bbracker
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a8e8cfb838
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switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv
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2022-03-01 03:11:43 +00:00 |
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David Harris
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02071700d6
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Removed Busybear dependencies
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2022-02-02 20:28:21 +00:00 |
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Ross Thompson
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5ce8dd60c5
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Fixed modelsim warning with linux simulation.
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2022-01-31 12:57:02 -06:00 |
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David Harris
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090533cfe9
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Replaced || and && with | and &
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2022-01-31 01:07:35 +00:00 |
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David Harris
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07425369fc
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Renamed wallypipelinedhart to wallypipelinedcore
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2022-01-20 16:02:08 +00:00 |
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David Harris
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1d8451c2cf
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Capitalized LSU and IFU, changed MulDiv to MDU
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2022-01-07 04:30:00 +00:00 |
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Ross Thompson
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77efcad15b
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Changed names of address in caches.
Removed old cache files.
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2022-01-05 22:19:36 -06:00 |
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David Harris
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85fa620cfb
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Finished removing generate statements
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2022-01-05 16:41:17 +00:00 |
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David Harris
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32590d484c
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Removed more generate statements
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2022-01-05 16:25:08 +00:00 |
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David Harris
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b36ace221e
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Renamed wally-pipelined to pipelined
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2022-01-04 19:47:41 +00:00 |
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