65 Commits

Author	SHA1	Message	Date
David Harris	cf03afa880	Eliminated flushing pipeline on CSR reads	2021-02-26 17:00:07 -05:00
David Harris	015b632eb1	Cleaned out unused signals	2021-02-26 09:17:36 -05:00
David Harris	d00d42cf9a	Merged bus into main	2021-02-25 00:28:41 -05:00
David Harris	f5e9c91193	All tests passing with bus interface	2021-02-24 07:25:03 -05:00
Ross Thompson	9b3637bd87	RAS needs to be reset or preloaded. For now I just reset it. ... Fixed bug with the instruction class. Most tests now pass. Only Wally-JAL and the compressed instruction tests fail. Currently the bpred does not support compressed. This will be in the next version.	2021-02-19 20:09:07 -06:00
Ross Thompson	5df7e959f3	Integrated the branch predictor into the hardward. Not yet working.	2021-02-17 22:19:17 -06:00
David Harris	8dec69c2ce	Added MUL	2021-02-15 22:27:35 -05:00
David Harris	2357f5513b	Debugging instruction fetch	2021-02-09 11:02:17 -05:00
David Harris	3551cc859b	Data memory bus integration	2021-02-07 23:21:55 -05:00
David Harris	d56d7a75a6	Rename ifu/dmem/ebu signals to match uarch diagram	2021-02-02 15:09:24 -05:00
David Harris	4fbb5f0f1b	Cleaned up hazard interface	2021-02-02 13:53:13 -05:00
David Harris	aad1d3d7dd	Moved writeback pipeline registers from datapth into DMEM and CSR	2021-02-02 13:02:31 -05:00
David Harris	9d7e242596	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
David Harris	056b147b13	Renamed DCU to DMEM	2021-02-01 18:52:22 -05:00
David Harris	396cea1ea7	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00