17 Commits

Author	SHA1	Message	Date
David Harris	de2a0da9e9	Reduced number of bits in mcause and medeleg registers	2023-03-29 07:02:09 -07:00
Ross Thompson	730f3ac84e	Fixed all tap/space issue in RTL.	2023-03-24 17:32:25 -05:00
David Harris	c4c7f5378e	Select original compressed or uncompressed instruction for MTVAL on illegal instruction fault	2023-03-22 06:29:30 -07:00
David Harris	77fb1b57f4	Fix Issue 145	2023-03-22 04:33:14 -07:00
David Harris	08ce265420	Replaced FenceM with InvalidateICacheM for event counting of fence.i	2023-03-18 09:24:31 -07:00
Ross Thompson	7dd8fa16c1	Renamed BTB misprediction to BTA.	2023-03-03 00:18:34 -06:00
Ross Thompson	bdab2c8506	Added divide cycle counter.	2023-03-02 23:59:52 -06:00
Ross Thompson	4b501f6e03	Added the i and d cache cycle counters.	2023-03-02 23:54:56 -06:00
Ross Thompson	b19d51b6a2	Added fence counter.	2023-03-02 23:29:20 -06:00
Ross Thompson	3dbfa96aef	Added csr write counter, sfence vma counter, interrupt counter, and exception counter.	2023-03-02 23:21:29 -06:00
Ross Thompson	cf4d8e6bd0	Added store stall to performance counters.	2023-03-02 23:10:54 -06:00
Ross Thompson	3d1ffac7d7	Cleaned up branch predictor performance counters.	2023-03-01 17:05:42 -06:00
Ross Thompson	2773048bd4	Name cleanup.	2023-02-28 17:48:58 -06:00
Ross Thompson	8af61c0cc0	Name changes to reflect diagrams.	2023-02-28 15:37:25 -06:00
Ross Thompson	e549bec060	Renamed signals to match new figures.	2023-02-24 19:51:47 -06:00
David Harris	0b9fd8a4b3	Fixed Issue #106: fld rasies load access fault instead of illegal instruction. The IEU controller had considered all fp loads and stores to be legal regardless of whether the FPU is enabled or the type is supported. Merged illegal instruction detection from both units into the Decode stage, saving two bits of pipeline register as well.	2023-02-21 09:32:17 -08:00
David Harris	99d179dd3e	Removed pipelined level of hierarchy	2023-02-02 14:14:11 -08:00