Ross Thompson
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a99c0502e5
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Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions.
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2021-03-24 15:56:55 -05:00 |
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Shreya Sanghai
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1d6a2989ed
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PC counts branch instructions
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2021-03-23 14:25:51 -04:00 |
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Shreya Sanghai
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bbe0957df5
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Merge branch 'gshare' into main
Conflicts:
wally-pipelined/regression/wave.do
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2021-03-18 17:25:48 -04:00 |
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Thomas Fleming
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8d484174a7
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-03-18 14:36:42 -04:00 |
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Thomas Fleming
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7f7597e667
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Connect tlb, pagetablewalker, and memory
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2021-03-18 14:35:46 -04:00 |
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Noah Boorstin
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bc1a0c6ee7
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change ifndef to generate/if
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2021-03-18 12:50:19 -04:00 |
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Shreya Sanghai
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08e9149e20
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made performance counters count branch misprediction
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2021-03-16 11:24:17 -04:00 |
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Shreya Sanghai
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74f1641c5a
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Merge branch 'counters' into main
added a configurable number of performance counters
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2021-03-16 11:01:30 -04:00 |
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Thomas Fleming
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be6ee84d87
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-03-05 15:46:51 -05:00 |
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Thomas Fleming
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7e11317a2d
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Export SATP_REGW from csrs to MMU modules
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2021-03-05 01:22:53 -05:00 |
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Noah Boorstin
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f48af209c4
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busybear: make CSRs only weird for us
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2021-03-05 00:46:32 +00:00 |
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Shreya Sanghai
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246dbd05e7
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fixed bugs
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2021-03-04 12:59:45 -05:00 |
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Shreya Sanghai
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f0ec365117
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added performance counters
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2021-03-04 11:42:52 -05:00 |
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Noah Boorstin
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bcc0010498
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Merge branch 'main' into busybear
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2021-02-28 20:45:08 +00:00 |
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Noah Boorstin
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a03796a519
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busybear: change sstatus, mstatus reset value
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2021-02-28 16:19:03 +00:00 |
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David Harris
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cf03afa880
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Eliminated flushing pipeline on CSR reads
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2021-02-26 17:00:07 -05:00 |
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David Harris
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015b632eb1
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Cleaned out unused signals
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2021-02-26 09:17:36 -05:00 |
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kaveh pezeshki
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c7863d58cd
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merged with main to integrate with AHB
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2021-02-26 05:37:10 -08:00 |
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David Harris
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c52a99ce2d
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Fixed fetch stall after jump in bus unit
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2021-02-23 09:08:57 -05:00 |
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Noah Boorstin
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5835641c6c
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busybear testbench: check (almost) all the CSRs
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2021-02-16 20:03:24 -05:00 |
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David Harris
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37dba8fd26
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More memory interface, ALU testgen
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2021-02-15 10:10:50 -05:00 |
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Noah Boorstin
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14cde0d59c
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Change CSR reset and available bits to conform to OVPsim
Now actually keeping perfectly in line with OVP for the first 100k instrs. Yay.
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2021-02-04 22:03:45 +00:00 |
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David Harris
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a44c2abb12
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Minor tweaks
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2021-02-02 19:44:37 -05:00 |
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David Harris
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d56d7a75a6
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Rename ifu/dmem/ebu signals to match uarch diagram
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2021-02-02 15:09:24 -05:00 |
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David Harris
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aad1d3d7dd
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Moved writeback pipeline registers from datapth into DMEM and CSR
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2021-02-02 13:02:31 -05:00 |
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David Harris
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9d7e242596
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Moved fpu to temporary location to fix compile and cleaned up interface formatting
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2021-02-01 23:44:41 -05:00 |
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David Harris
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396cea1ea7
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Reorganized src hierarchically
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2021-01-30 11:50:37 -05:00 |
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