11 Commits

Author	SHA1	Message	Date
bbracker	e7e4105931	* GPIO comprehensive testing ... * MEPC more aware if M stage has actually committed * UART interrupt testing progress * UART added read IIR side effect of lowering THRE intr	2021-06-08 12:32:46 -04:00
bbracker	2c77a13c08	fixed InstrValid signals and implemented less costly MEPC loading	2021-06-02 10:03:19 -04:00
Domenico Ottolia	d03ca20dc9	Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts	2021-04-29 20:42:14 -04:00
ushakya22	9dfbfd5772	fix to pcm bug	2021-04-29 15:21:08 -04:00
Thomas Fleming	da76b80991	Write PCM to TVAL registers	2021-04-22 16:17:57 -04:00
Domenico Ottolia	9f13ee3f31	Add tests for scause and ucause	2021-04-15 19:41:25 -04:00
Domenico Ottolia	92bb38fa8c	Add support for vectored interrupts	2021-04-15 19:13:42 -04:00
bbracker	8f7ddcfdff	rv64 interrupt servicing	2021-04-14 10:19:42 -04:00
David Harris	d56d7a75a6	Rename ifu/dmem/ebu signals to match uarch diagram	2021-02-02 15:09:24 -05:00
David Harris	9d7e242596	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
David Harris	396cea1ea7	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00