Ross Thompson
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0eceeeeeaa
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Simiplified global history branch predictor.
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2023-01-04 23:41:55 -06:00 |
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Kip Macsai-Goren
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ffae1c5ee6
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added fs=00 to status fp enabled test
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2022-12-22 15:15:53 -08:00 |
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Kip Macsai-Goren
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a768d70093
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Added status.tvm bit test that passes make and regression
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2022-12-22 14:43:22 -08:00 |
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Kip Macsai-Goren
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7aadf50f26
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updated trap handler alignemnts to 64 bytes in priv tests
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2022-12-22 14:23:04 -08:00 |
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David Harris
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c7f3aae084
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Only delegated bits of SIP are readable
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2022-12-21 12:32:49 -08:00 |
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Ross Thompson
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c3b43b2fac
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Waiting on fix for wally64periph uart test.
would like to remove vectored interrupt adder.
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2022-12-21 13:16:09 -06:00 |
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Ross Thompson
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0b4186f1e8
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Vectored interrupts now require 64 byte alignment.
Eliminates adder.
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2022-12-21 12:05:49 -06:00 |
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David Harris
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03c700d91c
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Restored rv32d arch test after new push
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2022-12-20 10:56:33 -08:00 |
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Ross Thompson
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4f56e6ff5d
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I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl.
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2022-12-18 18:30:35 -06:00 |
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Ross Thompson
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b4229c01ca
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Have a basic cache test to fill all ways and sets.
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2022-12-18 17:20:30 -06:00 |
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Ross Thompson
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376b01fcb8
|
Attempted to make a cache test.
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2022-12-18 17:15:08 -06:00 |
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Ross Thompson
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ebdac1a9d0
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Updated tests for fpga and BP.
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2022-12-18 16:24:26 -06:00 |
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David Harris
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5f637ef4a7
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Use FPU divider for integer division when F is supported
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2022-12-14 17:03:13 -08:00 |
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Kip Macsai-Goren
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2dfa426e10
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added passing GPIO test to 64 bit tests
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2022-12-05 21:31:00 -08:00 |
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Kip Macsai-Goren
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1d268fded4
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added corrrect scr read out of uart to periph test
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2022-12-05 20:16:02 -08:00 |
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Kip Macsai-Goren
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7411d50a78
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added all 32 bit tests to 64 bit periph tests except gpio
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2022-12-05 20:16:02 -08:00 |
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Kip Macsai-Goren
|
badc684f07
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added copies of 64 bit tests to 32 bit periph and priv tests
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2022-12-05 20:16:02 -08:00 |
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Kip Macsai-Goren
|
282d06b45f
|
added -01 to all WALLY tests
|
2022-12-05 20:16:02 -08:00 |
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Ross Thompson
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128b3d20e7
|
Updated riscv arch test removed misaligned1.
|
2022-12-04 00:18:10 +00:00 |
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Kip Macsai-Goren
|
af00eadec2
|
added tests for invalid address being written to satp. Not passing regression
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2022-11-27 13:22:35 -08:00 |
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Kip Macsai-Goren
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6fdd603ba1
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added potential fix to overrun error and fifo interrupt error. test passes
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2022-11-06 22:01:02 -08:00 |
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Kip Macsai-Goren
|
b42fc7ec6d
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fixed fifo timout handling. error now in data ready interrupt
|
2022-11-05 13:34:24 -07:00 |
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Kip Macsai-Goren
|
23268d22e5
|
fixed broken instructions so make works.
|
2022-11-03 23:06:20 +00:00 |
|
Ross Thompson
|
24cb36c38d
|
Updated to put dtb into the rodata segment for our linker script.
|
2022-11-03 17:48:20 -05:00 |
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Ross Thompson
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041ab8e401
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-03 17:36:04 -05:00 |
|
Ross Thompson
|
34cfc01d1c
|
Potentially a valid zero stage boot loader based on cva6.
|
2022-11-03 17:35:57 -05:00 |
|
Ross Thompson
|
f81d1e15b6
|
More outline for uart timeout interrupt.
|
2022-10-28 13:53:56 -05:00 |
|
Ross Thompson
|
372b9890ef
|
Untested change to uart test for outline of how to handle rx fifo timeout.
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2022-10-28 13:31:16 -05:00 |
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Kip Macsai-Goren
|
d4dd2dcc08
|
Added test for UART FIFO timeout. Does not pass regression
|
2022-10-25 05:35:56 +00:00 |
|
Ross Thompson
|
ae7a71c0f4
|
Created one off test to replicate the floating point forwarding hazard bug.
|
2022-10-22 16:29:12 -05:00 |
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Kip Macsai-Goren
|
d5cd67cf09
|
fixed endianness mstatush problem, passes make, not regression
|
2022-10-04 17:37:39 +00:00 |
|
Kip Macsai-Goren
|
0d2fcaeab1
|
added xlen and endianness test edits. xlen passes but endinanness still won't make
|
2022-09-26 05:03:19 +00:00 |
|
Kip Macsai-Goren
|
3f4c825a1a
|
added mstatus uxl, sxl bit tests (not tested in regression yet)
|
2022-09-18 00:11:29 +00:00 |
|
Kip Macsai-Goren
|
dda3b2d383
|
ported endianness tests to 32 bits (not tested in regression yet)
|
2022-09-18 00:10:29 +00:00 |
|
Kip Macsai-Goren
|
99596fac84
|
Fixed typos in existing endianness test
|
2022-09-18 00:09:52 +00:00 |
|
Kip Macsai-Goren
|
657e19df08
|
added full coverage of subword loads and stores to endianness test
|
2022-09-17 23:14:38 +00:00 |
|
Kip Macsai-Goren
|
a4fc5d3476
|
Created initial endianness tests
|
2022-09-16 01:06:26 +00:00 |
|
David Harris
|
8b8f045491
|
Completed PLIC-S tests. Regression working. This completes peripheral tests.
|
2022-08-03 09:33:56 -07:00 |
|
David Harris
|
62252c2167
|
Debugging plic-s test
|
2022-08-03 13:21:09 +00:00 |
|
David Harris
|
6ee8036ae7
|
plic-s debug
|
2022-08-03 12:33:09 +00:00 |
|
David Harris
|
e3ea86f984
|
Started plic-s tests
|
2022-08-03 03:48:08 +00:00 |
|
David Harris
|
d2de84a456
|
Added parity and stop bit tests to UART
|
2022-07-28 04:35:51 +00:00 |
|
David Harris
|
763a6d7340
|
Fixed UART reference output
|
2022-07-27 22:16:38 +00:00 |
|
David Harris
|
f61f0645fe
|
Finished UART test
|
2022-07-27 04:06:59 +00:00 |
|
David Harris
|
da275e3c26
|
Increased timeout threshold to avoid timeout building riscof tests on slow machine
|
2022-07-27 04:05:21 +00:00 |
|
slmnemo
|
a32698811d
|
Updated reference file for UART test
|
2022-07-26 09:39:31 -07:00 |
|
slmnemo
|
8141530f10
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-07-26 09:15:20 -07:00 |
|
slmnemo
|
528dfd9170
|
Committing changes made to UART test
|
2022-07-26 09:14:40 -07:00 |
|
David Harris
|
449c80b5f7
|
More work toward riscof tests
|
2022-07-26 06:19:13 -07:00 |
|
David Harris
|
539174f6f6
|
Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd
|
2022-07-25 16:23:10 -07:00 |
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