Ross Thompson
4f56e6ff5d
I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl.
2022-12-18 18:30:35 -06:00
Ross Thompson
ebdac1a9d0
Updated tests for fpga and BP.
2022-12-18 16:24:26 -06:00
Ross Thompson
73fd3fe040
Finally fixed the lru bug. It was actually a flush bug all along. At the end of flush writeback FlushAdr is incremented so clearly the dirty bit then clears the wrong set. Must either take an additional cycle to clear dirty and then change the address or clear the dirty bit before the cache bus acknowledgment. Changed it to clear at begining of that line's writeback before actually writting back.
2022-12-17 23:47:49 -06:00
Ross Thompson
cdeccd78e6
At long last found the subtle bug in the LRU.
...
Since the LRU memory is two ports, 1 read and 1 write, a write in cycle 1 to address x should not
forward data to a read from address y in cycle 2.
A read form address x in cycle 2 would still require forwarding.
2022-12-17 10:03:08 -06:00
Ross Thompson
731fbfc851
Oups found a bug with the new flush cache states.
2022-12-16 16:22:40 -06:00
Ross Thompson
b462554896
Cleanup of cache flush fsm enhancement.
2022-12-16 15:36:53 -06:00
Ross Thompson
e425ecac96
Fixed regression-wally to correct remove and mkdir wkdir.
2022-12-16 12:51:21 -06:00
David Harris
4365c99b52
Refactored stalls and flushes, including FDIV flush with FlushE
2022-12-15 10:56:18 -08:00
David Harris
5b040b7935
Regression delete wkdir files to prevent spurious failures
2022-12-15 10:24:58 -08:00
David Harris
f64c0589fe
FPU test list
2022-12-01 10:18:36 -08:00
Ross Thompson
f9ffcf377b
Reverted the IROM/DTIM address range modelsim assignment.
2022-11-30 17:13:33 -06:00
Ross Thompson
bfd238a4fc
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-30 13:30:37 -06:00
Ross Thompson
8692ccbafb
Intermediate commit. Replaced flip flop dirty bit array with sram.
2022-11-30 00:08:31 -06:00
cturek
e28a6901a9
div tests in sim-wally
2022-11-30 02:32:04 +00:00
Ross Thompson
1e2180ef98
Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.
2022-11-29 17:19:31 -06:00
Ross Thompson
179d321683
Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled.
2022-11-29 14:09:48 -06:00
Ross Thompson
ed54959378
Renamed signals in the cache.
2022-11-29 10:52:40 -06:00
Ross Thompson
4e52755c9f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-22 18:07:32 -06:00
cturek
3fbccbf119
Updated testbench/wave for fdivsqrt new start signals
2022-11-22 22:22:26 +00:00
Ross Thompson
84679c0062
Signal name changes for LRU.
2022-11-20 22:31:36 -06:00
Ross Thompson
1a00e7bbee
Changed names of cache signals.
2022-11-13 21:36:12 -06:00
Ross Thompson
5800dfde60
Updated wave file.
2022-11-13 21:34:45 -06:00
Ross Thompson
7311eca5ff
Wavefile update.
2022-11-10 15:48:06 -06:00
Ross Thompson
270a83352f
Found a way to remove the interlock fsm. Dramatically reducing the complexity of virtual memory and page table walks.
2022-10-23 13:46:50 -05:00
Ross Thompson
49a85c7f50
Sort of solved the bit width warning for dtim, irom ranges.
2022-10-19 10:42:19 -05:00
David Harris
6ab6467777
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-10-14 17:33:36 -07:00
David Harris
1428081742
Removed unused FPU waves
2022-10-14 17:33:32 -07:00
Ross Thompson
47915421c2
Fixed uncached read bug introduced by yesterday's changes.
2022-10-13 11:11:36 -05:00
Ross Thompson
403daecc8e
Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults.
...
The defaults are used for synthesis.
rv64i and rv32i: DTIM 2KiB, IROM 2KiB
rv32ic: DTIM 4KiB, IROM 16KiB
Regression tests require 8MiB or larger so modelsim overrides.
2022-10-11 10:47:13 -05:00
David Harris
36c0e1d4e9
Removed imperas tests from rv32i/rv64i because the configs lack privileged support expected in the tests. Also cleaned up comment in LSU
2022-10-10 10:22:12 -07:00
David Harris
e4c5754b3a
Made simple RV64 configuration be RV64i. Eliminated rv64ic and rv64fp. Fixed some bugs related to new width
2022-10-10 09:10:55 -07:00
Ross Thompson
b52f593ecb
Reorganized the configs.
2022-10-09 16:46:48 -05:00
Ross Thompson
8d01cf32fc
Updated wavefile.
2022-10-05 14:55:40 -05:00
Kip Macsai-Goren
c4441eb0fa
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2022-10-04 17:33:54 +00:00
Kip Macsai-Goren
175e824a61
Renamed endianswap to match module name
2022-10-04 17:33:49 +00:00
Ross Thompson
47e936cab3
Renamed signals in EBU.
2022-09-29 18:29:38 -05:00
David Harris
f08d5b23d5
Eliminated store after store stall when no cache; simplified divshiftcalc logic.
2022-09-21 13:02:34 -07:00
Ross Thompson
91fcca9d17
Merged together bram1p1rw with sram1p1rw as sram1p1rw.
...
Fixed a major issue with the real SRAM implemenation.
2022-09-21 12:20:00 -05:00
David Harris
8d1408a9d6
Moved fpu modules into subdirectories
2022-09-20 04:12:05 -07:00
David Harris
362056f53d
Removed unused otfc for Q
2022-09-19 00:43:27 -07:00
Ross Thompson
db56a326c9
renamed multimanager to multicontroller.
2022-09-14 14:03:37 -05:00
Ross Thompson
40e7d2648f
Renamed signals in the LSU.
2022-09-13 11:47:39 -05:00
David Harris
c2f81e309b
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-07 11:11:39 -07:00
David Harris
b0cf73d19c
Running 16-bit square root cases first in testfloat
2022-09-07 11:11:35 -07:00
Ross Thompson
fd4b382ec6
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-09-07 12:26:50 -05:00
Ross Thompson
54c55b57cb
Named change for ahb tests to be less annoying.
2022-09-07 12:24:41 -05:00
Ross Thompson
6581490f9c
Modified regression tests to add some ahb configurations.
2022-09-07 12:03:58 -05:00
David Harris
29f015810b
Added rv32i config for regression of wally32periph
2022-09-07 09:37:59 -07:00
Ross Thompson
d07c44bcf6
Merge branch 'multimanager' into main
2022-09-07 10:54:27 -05:00
David Harris
8438546d52
Fixed regression for divsqrt radix2
2022-09-07 06:12:23 -07:00
