bbracker
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0f394ba18b
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-06 07:50:57 -07:00 |
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bbracker
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0a8ce0593a
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filter traps list down to just interrupts
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2022-04-06 07:49:44 -07:00 |
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bbracker
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ea0471dcc7
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change RAM size in genInitMem.sh
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2022-04-06 07:49:04 -07:00 |
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Kip Macsai-Goren
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c3a6b88acc
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updated test signature locations
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2022-04-06 07:28:38 +00:00 |
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Kip Macsai-Goren
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590b86147b
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Updated trap handler to check interrupt vectoring before handling them and to use the mscratch instead of sp for a stack.
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2022-04-06 07:13:51 +00:00 |
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Kip Macsai-Goren
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3268f27f7a
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Updated PMA tests to comply with all width writes and reads to CLINT
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2022-04-06 07:13:51 +00:00 |
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Kip Macsai-Goren
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fbcb0c0bd8
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Added missing ZFH macro to new configs
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2022-04-06 07:13:51 +00:00 |
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David Harris
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7f462a6168
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-04-05 23:23:47 +00:00 |
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David Harris
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23da303ad3
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Added bootmem source ccode
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2022-04-05 23:22:53 +00:00 |
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Ross Thompson
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900939581e
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-05 15:42:07 -05:00 |
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Ross Thompson
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5faa88acd5
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Increazed fpga clock speed to 35Mhz.
linux boot is much faster.
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2022-04-05 15:09:49 -05:00 |
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David Harris
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171b943254
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Removed outdated sample testfloat calls
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2022-04-04 17:23:39 +00:00 |
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Katherine Parry
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c3d07b2c46
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generating all testfloat vectors
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2022-04-04 17:17:12 +00:00 |
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Ross Thompson
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91e99f0d34
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-04 10:56:10 -05:00 |
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Ross Thompson
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077beb18dd
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Constraint changes for 40Mhz wally.
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2022-04-04 10:50:48 -05:00 |
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Ross Thompson
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b77201143f
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Updated the bootloader to use the flash card divider. This will allow wally to run at a faster speed than flash.
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2022-04-04 10:38:37 -05:00 |
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Ross Thompson
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400b5f7632
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Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz.
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2022-04-04 09:57:26 -05:00 |
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Ross Thompson
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38160fe6ea
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-03 17:56:55 -05:00 |
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Ross Thompson
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3ebb7f1057
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fpga simulation works again.
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2022-04-03 17:31:07 -05:00 |
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Ross Thompson
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c4aadff487
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-03 17:30:47 -05:00 |
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David Harris
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fb95767da0
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Fixed bug with CSRRS/CSRRC for MIP/SIP
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2022-04-03 20:18:25 +00:00 |
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Ross Thompson
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3db60a1cc1
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-02 16:39:54 -05:00 |
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Ross Thompson
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2376d66ec2
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Added more ILA signals.
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2022-04-02 16:39:45 -05:00 |
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Ross Thompson
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35e8c6bb9c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-02 16:35:59 -05:00 |
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Kip Macsai-Goren
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ba7f976f92
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small bug fixes to 64 bit library
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2022-04-02 19:17:34 +00:00 |
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Kip Macsai-Goren
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7412979b71
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added unfinished tests to 32 bit library
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2022-04-02 19:15:07 +00:00 |
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Kip Macsai-Goren
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c056e0dc5f
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updated 32 bit tests to be in line with 64 bit test library
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2022-04-02 19:14:12 +00:00 |
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Kip Macsai-Goren
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25984d1643
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removed compressed instructions from privileged tests
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2022-04-02 19:12:44 +00:00 |
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Kip Macsai-Goren
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37c755e6ce
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added RV64IA config to have a config without compressed instructions
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2022-04-02 18:24:08 +00:00 |
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Ross Thompson
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691f1a6b0d
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-01 17:18:25 -05:00 |
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Ross Thompson
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51dfa16f59
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Updated the fpga test bench.
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2022-04-01 17:14:47 -05:00 |
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Ross Thompson
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48c49802b2
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Fixed linting issues.
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2022-04-01 15:20:45 -05:00 |
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Ross Thompson
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301f20052b
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-01 12:50:34 -05:00 |
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Ross Thompson
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19a8df9739
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Added wave config
added new signals to ILA.
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2022-04-01 12:44:14 -05:00 |
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David Harris
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61e1758a69
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-04-01 16:49:18 +00:00 |
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David Harris
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c6960ede37
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Changed Linux disassembly to -S to preserve source code lines
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2022-04-01 16:49:13 +00:00 |
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bbracker
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9d26bfe71d
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expand WALLY-PERIPH test to use SEIP on PLIC context 1
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2022-03-31 18:02:06 -07:00 |
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bbracker
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e09079d8b4
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-31 17:54:43 -07:00 |
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bbracker
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55df8bc3f7
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fix lingering overrun error bug
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2022-03-31 17:54:32 -07:00 |
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Ross Thompson
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48c862d536
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Added PLIC to ILA.
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2022-03-31 16:44:49 -05:00 |
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Ross Thompson
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da93d14050
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-31 16:30:55 -05:00 |
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Ross Thompson
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b5cdf035fc
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-31 15:50:04 -05:00 |
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Ross Thompson
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ade4a4cd5e
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Notes on what to change in ram.sv.
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2022-03-31 15:48:15 -05:00 |
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bbracker
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bdb3417656
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-31 13:46:32 -07:00 |
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bbracker
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0f7e995055
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simplify plic logic
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2022-03-31 13:46:24 -07:00 |
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David Harris
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c7043e4d63
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Added SystemVerilog flag to fma.do so that fma16 compiles properly
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2022-03-31 17:00:38 +00:00 |
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Ross Thompson
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88c5cdc873
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-31 11:39:41 -05:00 |
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Ross Thompson
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bf9683f0d2
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Forced to go back to hard coded preload.
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2022-03-31 11:39:37 -05:00 |
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Ross Thompson
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54001222cf
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-31 11:38:55 -05:00 |
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Ross Thompson
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285fc6fd4d
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Modified clint to support all byte write sizes.
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2022-03-31 11:31:52 -05:00 |
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