Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity
4,608 Commits 14 Branches 1 Tag 31 MiB
0dc09ac22d
Commit Graph

53 Commits

Author SHA1 Message Date
Ross Thompson
e774dd2db9 Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage. 2022-12-15 09:53:35 -06:00
David Harris
33aca5d35e Added IDIV_ON_FPU flag to control whether integer division uses FPU 2022-12-15 06:37:55 -08:00
David Harris
5f637ef4a7 Use FPU divider for integer division when F is supported 2022-12-14 17:03:13 -08:00
David Harris
9395414df3 Renamed FPUStallD to FCvtIntStallD 2022-12-02 11:55:23 -08:00
David Harris
f08d5b23d5 Eliminated store after store stall when no cache; simplified divshiftcalc logic. 2022-09-21 13:02:34 -07:00
Ross Thompson
c6927d2ace Modified the lsu/ifu memory configurations. 2022-08-24 12:35:15 -05:00
David Harris
8b2e368805 Only stall FPU to IEU on convert instructions with dependencies 2022-08-23 12:57:18 -07:00
David Harris
113258a0d0 Cleaned up fcvt selection control to IEU and FPUIllegalInst signals 2022-08-23 12:17:19 -07:00
David Harris
69be6d0873 Simplify IEU-FP datapath 2022-08-23 11:16:36 -07:00
David Harris
34eece10b8 Finished FPU-LSU interface cleanup 2022-08-22 13:43:04 -07:00
David Harris
2170203847 Simplified FPU-LSU interface to skip IEU 2022-08-22 13:28:51 -07:00
David Harris
564281b8c1 Removed 2-cycle FPU-IEU latency stall 2022-08-22 16:14:15 +00:00
David Harris
b91f33372e Commented out unused comparators 2022-08-22 08:28:28 +00:00
Katherine Parry
6baded9121 added rv32 double precision stores - untested 2022-06-28 21:33:31 +00:00
Madeleine Masser-Frye
0161683945 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-06-21 20:31:06 +00:00
Madeleine Masser-Frye
fe31ee92e8 switched comparator to dc flip version 2022-06-21 20:30:33 +00:00
Katherine Parry
254ebf478e added fld in rv32 - needs testing 2022-06-20 22:53:13 +00:00
Katherine Parry
31fd8772cf postprocessing unit created and passing all tests 2022-06-13 22:47:51 +00:00
David Harris
1d8bc2dc1b Added stalls for pending SFENCE.VMA and FENCE.I in hazard unit 2022-06-02 09:37:59 -07:00
David Harris
faa15b1f8d Cleaned up comments in controller 2022-06-02 15:48:33 +00:00
David Harris
4237bb7abd Added comments to some files, added a+b = 0 detector to comparator.sv 2022-05-28 09:41:48 +00:00
David Harris
e81e530f68 More signal cleanup 2022-05-12 15:39:44 +00:00
David Harris
4edf9b6355 More unused signal cleanup 2022-05-12 15:15:30 +00:00
David Harris
1f761c4e06 PPA script progress 2022-05-11 18:11:51 +00:00
David Harris
4b91fddc0a Illegal instruction fault when running FPU instruction with STATUS_FS = 0 2022-05-03 18:32:01 +00:00
David Harris
1166c40059 FPU generates illegal instruction if MSTATUS.FS = 00 2022-05-03 11:56:31 +00:00
David Harris
bcd8728b3e Switched to behavioral comparator for best PPA 2022-05-03 11:00:39 +00:00
David Harris
b4a422f771 Comparator experiments 2022-05-03 10:54:30 +00:00
David Harris
6bb4cd1bca Prefix comparator cleanup 2022-04-17 21:53:11 +00:00
David Harris
5bb521635e Experiments with prefix comparator; minor fixes in WFI and testbench warnings 2022-04-17 21:43:12 +00:00
David Harris
d71940d96d Simplified SLT logic 2022-04-17 16:49:51 +00:00
Ross Thompson
71aad2d213 Moved WriteDataM register into LSU. 2022-03-23 14:17:59 -05:00
David Harris
2cea3349ad LSU/Cache code review notes 2022-03-04 00:07:31 +00:00
David Harris
329fea9329 Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath 2022-02-28 20:50:51 +00:00
David Harris
799736632b Register file comments about reset 2022-02-16 17:21:05 +00:00
David Harris
a34cbdb7d0 Synthesis script cleanup, eliminated privileged instructiosn from controller when ZICSR_SUPPORTED = 0 2022-02-12 05:50:34 +00:00
David Harris
de5e80696d Cleaned up synthesis warnings 2022-02-11 01:15:16 +00:00
David Harris
9b55848ffc Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration 2022-02-06 01:22:40 +00:00
David Harris
4d09510af9 cacheway cleanup 2022-02-03 16:07:55 +00:00
David Harris
7f237220dd cacheway cleanup 2022-02-03 16:00:57 +00:00
David Harris
da8819d64b changed DMEM and IMEM configurations to support BUS/TIM/CACHE 2022-02-03 00:41:09 +00:00
Ross Thompson
4a75e69457 Merged in the debug ila updates. 2022-01-18 17:29:21 -06:00
David Harris
55b4423329 Added E extension, and downloaded riscv-dv and embench-iot to addins 2022-01-17 14:42:59 +00:00
David Harris
120fb7863f Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
David Harris
1d8451c2cf Capitalized LSU and IFU, changed MulDiv to MDU 2022-01-07 04:30:00 +00:00
David Harris
0e023e29d8 Code cleanup 2022-01-07 04:07:04 +00:00
David Harris
2b8e8707a7 Floating point test cleanup 2022-01-06 21:45:16 +00:00
David Harris
55e757db03 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-06 18:10:32 +00:00
David Harris
c9aa21d5a3 FPU debug and configurable logic cleanup 2022-01-06 18:10:25 +00:00
Ross Thompson
3517db6b64 Fixed xilinx synth error with $error in extend.sv 2022-01-05 17:48:08 -06:00