David Harris
0c459e5edd
Merge pull request #270 from liamchalk00/main
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pmpcfg test cases
2023-04-22 08:41:11 -07:00
Liam
2ed9384238
pmpcfg test cases
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Increased IFU coverage from 83.37% to 83.53% and LSU coverage from 93.14% to 93.28%.
2023-04-21 20:43:37 -07:00
Ross Thompson
884c3c22d5
Merge pull request #266 from davidharrishmc/dev
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FDivSqrt cleanup
2023-04-21 20:23:23 -05:00
David Harris
e11212598f
fdivsqrt cleanup
2023-04-20 17:35:01 -07:00
David Harris
f9ca280e01
continued cleanup
2023-04-20 16:48:23 -07:00
David Harris
ea7c50e0ee
Reordered fdivsqrtpreproc to follow logic
2023-04-20 16:38:47 -07:00
David Harris
ca0269c094
Started fdivsqrtpreproc flow organization
2023-04-20 16:25:19 -07:00
David Harris
c431278fe6
Fmv h/q comments in controller
2023-04-20 16:24:58 -07:00
David Harris
b8c2062698
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-04-20 16:07:37 -07:00
David Harris
94d1533264
Merge pull request #256 from cturek/main
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Simplifying fds to follow diagram
2023-04-20 16:07:22 -07:00
David Harris
0fddad2fd4
Merge pull request #265 from Noah-G-L/main
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Add Coverage for TLB, MP, Global, ASID and Match
2023-04-20 16:06:09 -07:00
Noah Limpert
cf150a2ea9
Add in a test that makes match 3 = 0 for all tlb lines
2023-04-20 14:50:06 -07:00
Noah Limpert
73cca666bf
Commiting changes to add coverage to ASID, Global, Megapage size checks.
2023-04-20 14:38:13 -07:00
David Harris
870c15c4f5
Update README.md
2023-04-20 14:15:34 -07:00
David Harris
5f14dfe748
Update README.md
2023-04-20 14:09:32 -07:00
Ross Thompson
ffa686a605
Merge pull request #264 from davidharrishmc/dev
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Added -fp flag to run arch64d/f tests in coverage
2023-04-20 09:26:16 -05:00
David Harris
9fac2b6e57
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-04-19 14:50:09 -07:00
David Harris
24e60c232d
Merge pull request #262 from SydRiley/main
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removed comments for fixed bugs in fpu, increased coverage in fpu, ifu, and lsu: fpu from 93.51% to 93.62%, ifu from 78.56% to 78.75%, lsu from 88.96% to 88.98%
2023-04-19 14:49:50 -07:00
Sydeny
039a06ec95
clarifying comments in exclusions
2023-04-19 14:47:34 -07:00
Sydeny
b76ed145e6
removed comments for fixed bugs in fpu, increased coverage: fpu from 93.51% to 93.62%, ifu from 78.56% to 78.75%, lsu from 88.96% to 88.98%
2023-04-19 13:30:12 -07:00
David Harris
a3f3967f59
Added -fp flag to run arch64d/f tests in coverage
2023-04-19 13:07:07 -07:00
David Harris
a4cc3c6b3e
Merge pull request #261 from liamchalk00/main
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Add pmpcfg test cases increasing IFU coverage
2023-04-19 12:37:19 -07:00
Liam
2684a81754
Add pmpcfg test cases increasing IFU coverage
2023-04-19 11:58:22 -07:00
David Harris
68295bd750
Update tests.vh
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Missing comma from merge
2023-04-19 06:23:05 -07:00
David Harris
5ac756b685
Merge pull request #259 from AlecVercruysse/coverage4
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D$ Coverage
2023-04-19 06:17:01 -07:00
David Harris
79dbfae4af
Merge branch 'main' into coverage4
2023-04-19 06:16:07 -07:00
David Harris
c36d3cb32b
Merge pull request #258 from liamchalk00/main
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Add test cases for pmpcfg.S
2023-04-19 04:52:59 -07:00
David Harris
59d153ace0
Merge branch 'main' into main
2023-04-19 04:50:12 -07:00
David Harris
2beb32e6b9
Merge pull request #257 from koooo142857/main
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PMPCFG_ARRAY_REGW cases
2023-04-19 04:47:12 -07:00
David Harris
a13feb5d0b
Merge branch 'main' into main
2023-04-19 04:46:51 -07:00
David Harris
f4a949c28c
Merge pull request #255 from kjprime/main
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Add PR#252 test file to coverage
2023-04-19 04:43:25 -07:00
Alec Vercruysse
7ba2bfd4b6
CacheFSM logic simplification for AMO operations
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Ran this by Ross.
2023-04-19 01:34:01 -07:00
Alec Vercruysse
b52512b1ae
D$ scope-specific coverage exclusions (I$ logic that never fires)
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The InvalidateCache signal in the D$ is for I$ only, which
causes some coverage issues that need exclusion.
Another manual exclusion is due to the fact that D$ writeback, flush,
write_line, or flush_writeback states can't be cancelled by a flush,
so those transistions are excluded.
There is some other small stuff to review (logic simplification,
or an exclusion pragma if removing the redundent logic would
make it harder to understand the code, as is the case in the
FlushAdrCntEn assign statement, in my opinion).
2023-04-19 01:34:01 -07:00
Alec Vercruysse
3de03abd9d
add D$ test case to trigger a FlushStage while SetDirtyWay=1
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This hits some conditional coverage in each cacheway.
A cache store hit happens at the same time as a StoreAmoMisalignedFault.
2023-04-19 01:34:01 -07:00
Alec Vercruysse
cd9feb0260
Cover CacheWay edge case: CacheDataMem we=1 while ce=0.
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This test basically triggers an i$ miss during a d$ (hit) store
operation. It requires some tricky timing (e.g. a flushD right
before the relevant store). I use a script to generate the test.
2023-04-19 01:34:01 -07:00
Alec Vercruysse
e3593800d9
fix unhit exclusion in fdivsqrtfsm
2023-04-19 01:34:01 -07:00
Liam
2a4bc01944
Update tests.vh
2023-04-18 23:15:47 -07:00
Liam
777028e43b
Add test cases for pmpcfg.S
2023-04-18 23:06:52 -07:00
Kevin Wan
fe51108740
a
2023-04-18 22:09:50 -07:00
Kevin Wan
fed7681695
Merge branch 'main' of https://github.com/koooo142857/cvw into main
2023-04-18 21:55:06 -07:00
koooo142857
ea39b53c97
Merge branch 'openhwgroup:main' into main
2023-04-18 21:53:46 -07:00
Kevin Wan
20a0803f46
Completely covers all PMPCFG_ARRAY_REGW cases
2023-04-18 21:50:48 -07:00
Kevin Wan
3ef81f4e6a
PMPCFG_ARRAY_REGW cases
2023-04-18 18:43:50 -07:00
Cedar Turek
30bd1e2a33
created fdivsqrtcycles, moved cycles calculation from FSM to preproc
2023-04-18 16:14:45 -07:00
Kevin Thomas
385564fe4c
Add PR#252 test file to coverage
2023-04-18 17:57:56 -05:00
Cedar Turek
871d495ca1
gave integer bits to D instead of adding manually everywhere
2023-04-18 15:41:04 -07:00
Cedar Turek
054c8d638c
moved D flop to preproc
2023-04-18 15:14:17 -07:00
David Harris
d5e2fefe2c
Merge pull request #252 from mcook26/main
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Increase of TLB coverage in IFU
2023-04-18 05:49:18 -07:00
Miles Cook
5cfd0577d1
Increase of TLB coverage in IFU
2023-04-17 18:35:03 -07:00
Sydeny
f0ff1a4447
increasing lsu coverage by excluding the pmachecher/adrdecs/clintdec or uncoreram signal SizeValid becauseany size is valid so signal is always 1
2023-04-17 14:19:48 -07:00