Ross Thompson
09ff5c2c45
Updated debug2.xdc ila constraints to match rtl.
2022-03-28 10:52:26 -05:00
Ross Thompson
5394e79ad7
Fixed ila's config.
2022-02-11 13:58:45 -06:00
Ross Thompson
44d4e08009
Fixed debug2.xdc to match wally changes.
2022-02-08 15:23:44 -06:00
Ross Thompson
3b31d8f8fb
Updated debug2 ila signal names.
2022-01-28 11:43:49 -06:00
Ross Thompson
862bf2faae
Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
2022-01-27 17:11:27 -06:00
Ross Thompson
840e814e95
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-25 19:21:04 -06:00
Ross Thompson
d46bc94119
Added pin location for reset on VCU118 board. Somehow this was missing and still worked.
2022-01-25 17:48:42 -06:00
David Harris
07425369fc
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
Ross Thompson
acec56c27e
Added PCNextF and PostSpillInstrRawF to ila.
2022-01-19 14:05:14 -06:00
Ross Thompson
c913a3ceeb
Fixed fpga ila debug to match lsu changes.
2022-01-18 21:13:18 -06:00
Ross Thompson
4a75e69457
Merged in the debug ila updates.
2022-01-18 17:29:21 -06:00
David Harris
6febce0001
Moved Dcache into bus block
2022-01-15 00:39:07 +00:00
David Harris
fd13272d4c
Renamed LSUStall to LSUStallM
2022-01-15 00:24:16 +00:00
Ross Thompson
11f1613d59
Added additional fsm to ILA.
2022-01-12 14:17:16 -06:00
Ross Thompson
d8173745bb
Possible fix for the TrapM DTLBMiss suppression.
2022-01-12 14:17:16 -06:00
Ross Thompson
d14dffd010
Updated debug constraints again to match changes in verilog.
2022-01-08 13:28:51 -06:00
Ross Thompson
6bd447d570
Patched the ILA's debug2.xdc constraint file to work with the wally memory design.
2022-01-06 15:18:18 -06:00
Ross Thompson
42623141cd
Updated fpga ILA constraints to match the new changes to the rtl.
2022-01-06 11:56:09 -06:00
Ross Thompson
5a2ae561a7
Updates to support fpga.
2022-01-05 18:07:23 -06:00
Ross Thompson
beb1988539
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-20 10:03:19 -06:00
Ross Thompson
225cd5a114
Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache.
2021-12-19 14:00:30 -06:00
Ross Thompson
a11597b6bd
Added more debugging code for FPGA.
2021-12-17 14:40:25 -06:00
Ross Thompson
21b13fc237
Reverted 23Mhz to 10Mhz. The flash card can't work at that speed.
...
added icache debugging signals.
2021-12-15 10:24:29 -06:00
Ross Thompson
af9f97454d
Cleaned up fpga synthesis script.
2021-12-13 18:26:54 -06:00
Ross Thompson
68745d40f2
Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language.
2021-12-12 17:21:44 -06:00
Ross Thompson
f2628494e3
Missed constraints file for xilinx ILA.
2021-12-12 15:06:29 -06:00
Ross Thompson
c3c9c327b7
Fixed more constraint issues in fpga.
...
Added back in the ILA.
Design does not work yet. Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
2021-12-05 15:14:18 -06:00
Ross Thompson
5b4ff4526e
Fixed a bunch of fpga issues.
2021-12-03 17:47:54 -06:00
Ross Thompson
96fb3acefd
Constraints for fpga are still wrong.
2021-12-02 14:23:21 -06:00
Ross Thompson
0d47749cb5
Separated timing constraints from ILA.
2021-12-01 18:15:04 -06:00
Ross Thompson
e94fb2aaec
Got fpga synthesis running from scripts.
2021-12-01 16:59:04 -06:00
