forked from Github_Repos/cvw
		
	| Added back in the ILA. Design does not work yet. Stil having issues with order of automatic clock and I/O constraint ordering. Added back in the preload for the boottim. | ||
|---|---|---|
| .. | ||
| constraints.xdc | ||
| debug.xdc | ||
| Added back in the ILA. Design does not work yet. Stil having issues with order of automatic clock and I/O constraint ordering. Added back in the preload for the boottim. | ||
|---|---|---|
| .. | ||
| constraints.xdc | ||
| debug.xdc | ||