bbracker
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7af81d93ec
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greatly improve trace-generating checkpoint process with QEMU hack
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2022-02-28 23:00:00 +00:00 |
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David Harris
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0cc09ed918
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Enhanced printing intermediate results in fpcalc.c
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2022-02-28 04:15:20 +00:00 |
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David Harris
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50f5607799
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New softfloat_calc program
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2022-02-27 20:35:01 +00:00 |
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David Harris
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f4be78ecc3
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Created softfloat_demo showcasing how to do math with SoftFloat
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2022-02-27 18:17:21 +00:00 |
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bbracker
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8518fd44a5
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revived checkpointing and hacked it up to generate a trace starting at the checkpoint
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2022-02-25 23:51:40 +00:00 |
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Ross Thompson
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f12874ef80
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Ignore saif files.
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2022-02-09 19:30:26 -06:00 |
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bbracker
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fd4556393b
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rename dump-dts debug script
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2022-02-10 00:10:09 +00:00 |
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Ross Thompson
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5a654a2874
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Cleaned up synthesis flow.
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2022-02-09 15:18:49 -06:00 |
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bbracker
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b0fda60cf7
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gitignore dtb's because we only care about dts's as being source files
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2022-02-08 11:14:59 +00:00 |
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bbracker
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f94e5560ac
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add trimmed-down virt devicetree to repo for QEMU
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2022-02-08 11:11:44 +00:00 |
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David Harris
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f1c8f5dda4
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ignore .sv files in synthDC/hdl
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2022-02-04 00:57:13 +00:00 |
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David Harris
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f27961f54b
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examples cleanup
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2022-02-02 12:57:13 +00:00 |
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David Harris
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090533cfe9
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Replaced || and && with | and &
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2022-01-31 01:07:35 +00:00 |
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David Harris
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748375c82f
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Updated configs to fix GPIO address to match FU540
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2022-01-26 18:16:34 +00:00 |
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David Harris
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bd320c2f76
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lsu cleanup down to 346 lines
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2022-01-15 01:19:44 +00:00 |
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David Harris
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b36ace221e
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Renamed wally-pipelined to pipelined
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2022-01-04 19:47:41 +00:00 |
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David Harris
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3bd9343013
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Fixed .gitignore
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2021-12-29 18:58:36 +00:00 |
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Ross Thompson
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ca404746ec
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Updated .gitignore file to hide fpga outputs.
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2021-12-13 18:30:10 -06:00 |
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David Harris
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f45fe48158
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-04 20:26:01 -08:00 |
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David Harris
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64f33161bc
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Added files to repo
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2021-12-04 20:25:33 -08:00 |
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Ross Thompson
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d5f445e0fd
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Added make clean to fpga IP generator.
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2021-11-29 18:42:28 -06:00 |
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Ross Thompson
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a528a86607
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Created Makefile to manage IP generation.
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2021-11-29 18:33:58 -06:00 |
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bbracker
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526aff54a8
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linux testgen refactor
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2021-11-01 14:09:49 -07:00 |
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bbracker
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af998e3e27
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gitignore the addins folder because it contains external repos
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2021-10-19 13:32:26 -07:00 |
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bbracker
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bfe972a213
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gitignore new logs folder
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2021-10-12 10:42:13 -07:00 |
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bbracker
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8d65d50085
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separated buildroot debugging from buildroot logging
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2021-07-17 14:52:34 -04:00 |
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bbracker
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335afb14e7
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testvector unlinker for dev purposes
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2021-07-14 11:05:34 -04:00 |
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bbracker
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28887bb3d5
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needed to create a directory for gdb script
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2021-07-13 19:39:57 -04:00 |
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bbracker
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3565580f40
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updated buildroot make procedure to incorporate configs more robustly
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2021-07-13 12:40:14 -04:00 |
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bbracker
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1f52a2f938
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organize/update buildroot scripts for new image
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2021-07-09 17:03:47 -04:00 |
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bbracker
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44a48cf28d
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organize linux-testgen folder, add readme to describe Buildroot process, add Buildroot config source files
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2021-07-08 19:18:11 -04:00 |
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bbracker
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74833dc68c
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split intermediate GDB output file into smaller files for better debug experience
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2021-06-26 07:18:26 -04:00 |
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bbracker
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2d9c91096b
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make linux testgen be nohup-friendly and make parser account for lr/sc memory accesses
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2021-06-24 08:35:00 -04:00 |
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bbracker
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9b27cd6fb7
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added slack notifier for long sims
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2021-06-22 08:31:41 -04:00 |
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bracker
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26512348b0
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gitignore merge
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2021-06-18 21:12:05 -05:00 |
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bracker
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34f17b90ea
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handle tera usernames more gracefully
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2021-06-18 21:11:14 -05:00 |
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bbracker
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1781ae9c93
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on-Tera solution for sym linking to linux testvectors
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2021-06-18 22:01:18 -04:00 |
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bracker
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cd7d403f92
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-06-18 20:41:01 -05:00 |
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bracker
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0addf4a297
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script support for copying large files from tera
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2021-06-18 20:40:19 -05:00 |
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bbracker
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6625f74a85
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still not sure if QEMU workaround is correct, but here is all linux progress so far
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2021-06-17 00:50:02 -04:00 |
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bbracker
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2feb9309bb
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script for running make and logging output
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2021-05-17 22:12:18 -04:00 |
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Ross Thompson
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6e803b724e
|
Merge branch 'tests' into icache-almost-working
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2021-04-25 21:25:36 -05:00 |
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Noah Boorstin
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0fa32ae5d6
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buildroot parser: more updates
5 -> 23 instructions!
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2021-04-17 17:44:46 -04:00 |
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Ross Thompson
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a64a37d702
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Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.
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2021-03-30 23:18:20 -05:00 |
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Noah Boorstin
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d02c88dab5
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busybear: stop NOPing out atomics
and bump regression to check for 800k instrs, up from 200k
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2021-03-25 13:29:56 -04:00 |
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Thomas Fleming
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7367052e76
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Add vscode and pycache folders to .gitignore
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2021-03-25 02:37:50 -04:00 |
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bbracker
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717257d9ac
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gitignore FunctionRadix.addr
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2021-03-25 00:13:46 -04:00 |
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Ross Thompson
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f92f766573
|
Added debug option to disable the function radix if not needed.
Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests.
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2021-03-10 15:17:02 -06:00 |
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Noah Boorstin
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1858c32e9d
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add .nfs* files to gitignore
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2021-02-28 20:48:01 +00:00 |
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Jarred Allen
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8dcb4b2d57
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Add the regression logs and new regression byproducts to the gitignore
|
2021-02-02 10:43:41 -05:00 |
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