forked from Github_Repos/cvw
64 lines
1.4 KiB
Plaintext
64 lines
1.4 KiB
Plaintext
**/work*
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**/wally_*.log
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.nfs*
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__pycache__/
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.vscode/
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#External repos
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addins
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addins/riscv-arch-test/Makefile.include
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addins/riscv-tests/target
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#vsim work files to ignore
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transcript
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vsim.wlf
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pipelined/wlft*
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wlft*
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/imperas-riscv-tests/FunctionRadix_32.addr
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/imperas-riscv-tests/FunctionRadix_64.addr
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/imperas-riscv-tests/FunctionRadix.addr
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/imperas-riscv-tests/ProgramMap.txt
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/imperas-riscv-tests/logs
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*.o
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*.d
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*.vstf
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testsBP/*/*/*.elf*
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testsBP/*/OBJ/*
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testsBP/*/*.a
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tests/wally-riscv-arch-test/riscv-test-suite/*/I/*/*
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tests/linux-testgen/linux-testvectors/*
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!tests/linux-testgen/linux-testvectors/tvCopier.py
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!tests/linux-testgen/linux-testvectors/tvLinker.sh
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!tests/linux-testgen/linux-testvectors/tvUnlinker.sh
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tests/linux-testgen/buildroot
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tests/linux-testgen/buildroot-image-output
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tests/linux-testgen/buildroot-config-src/main.config.old
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tests/linux-testgen/buildroot-config-src/linux.config.old
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tests/linux-testgen/buildroot-config-src/busybox.config.old
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pipelined/regression/slack-notifier/slack-webhook-url.txt
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pipelined/regression/logs
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fpga/generator/IP
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fpga/generator/vivado.*
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fpga/generator/.Xil/*
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fpga/generator/WallyFPGA*
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fpga/generator/reports/
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fpga/generator/*.log
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fpga/generator/*.jou
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*.objdump*
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*.signature.output
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examples/asm/sumtest/sumtest
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examples/asm/example/example
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examples/C/sum/sum
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examples/C/fir/fir
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linux/devicetree/debug/*
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!linux/devicetree/debug/dumpdts.sh
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*.dtb
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synthDC/WORK
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synthDC/alib-52
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synthDC/*.log
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synthDC/*.svf
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synthDC/runs/
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synthDC/hdl
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