Kip Macsai-Goren
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bd87af478a
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Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address)
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2022-04-22 22:46:11 +00:00 |
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bbracker
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9eec1a83a6
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deprecate unused LINUX_FIX_READ macro
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2022-04-21 19:14:47 -07:00 |
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bbracker
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9c1e398bb5
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change how tristate I/O is spoofed in GPIO loopback test
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2022-04-21 10:31:16 -07:00 |
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Ross Thompson
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e56b9f18d5
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-21 09:52:42 -05:00 |
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Ross Thompson
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a86274a1e0
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Modified wally-pipelined.do for no trace linux sim.
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2022-04-21 09:52:33 -05:00 |
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David Harris
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1e19cf9f14
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Simplified profile for UART boot; added warnings on UART Rx errors
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2022-04-21 04:54:45 +00:00 |
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Kip Macsai-Goren
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25d0f6305a
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added new tests to tests.vh
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2022-04-20 17:34:40 +00:00 |
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Kip Macsai-Goren
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8e72ace5ac
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fixed rv32ia to support clint and GPIO for priv tests
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2022-04-20 17:31:34 +00:00 |
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Kip Macsai-Goren
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324d3fcea5
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added working general trap tests to regression
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2022-04-20 06:48:01 +00:00 |
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Ross Thompson
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b94927d8a6
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-19 14:09:50 -05:00 |
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David Harris
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c57b9e6703
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Added baby torture tests
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2022-04-19 15:13:06 +00:00 |
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David Harris
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eaa0d44980
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Fixed WFI decoding in IFU
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2022-04-18 19:02:08 +00:00 |
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Kip Macsai-Goren
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ced763beb6
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Added GPIO loopback to let outputs cause interrupts
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2022-04-18 07:22:49 +00:00 |
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Kip Macsai-Goren
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121cc627f6
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Added working trap test to regression, fixed hanfling of some interrupts
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2022-04-18 07:22:16 +00:00 |
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Shreya Sanghai
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6f0085201b
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replaced k with bpred size
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2022-04-18 04:21:03 +00:00 |
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Shreya Sanghai
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a8b3cc8cf9
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added bpred size to wally config
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2022-04-18 04:21:03 +00:00 |
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David Harris
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22842816a8
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LSU name cleanup
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2022-04-18 03:18:38 +00:00 |
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Ross Thompson
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61dbf13a69
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Fixed bug I introduced by csrc cleanup and changes to ILA.
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2022-04-17 21:45:46 -05:00 |
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David Harris
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e04febdb57
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-04-18 01:30:11 +00:00 |
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David Harris
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c07b9d1722
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Renamed FinalAMOWriteDataM to AMOWriteDataM
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2022-04-18 01:30:03 +00:00 |
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David Harris
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6504017044
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Run 4M instructions in buildroot test to get through kernel & VirtMem startup
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2022-04-18 01:29:38 +00:00 |
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Ross Thompson
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a5d4e39e7d
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Added back the instret counter to ILA.
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2022-04-17 18:44:07 -05:00 |
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Ross Thompson
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3add26be64
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fixed no forcing bug in linux testbench.
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2022-04-17 17:49:51 -05:00 |
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David Harris
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d8b4c985cd
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Remvoed bytemask anding from FinalWriteDataM in subwordwrite
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2022-04-17 22:33:25 +00:00 |
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David Harris
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6bb4cd1bca
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Prefix comparator cleanup
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2022-04-17 21:53:11 +00:00 |
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David Harris
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5bb521635e
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Experiments with prefix comparator; minor fixes in WFI and testbench warnings
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2022-04-17 21:43:12 +00:00 |
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Kip Macsai-Goren
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331efcedc4
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added new tests to makefrag and tests.vh
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2022-04-17 21:00:36 +00:00 |
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Ross Thompson
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5a6ad32688
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-17 15:23:46 -05:00 |
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Ross Thompson
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7135364d1a
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Increased uart baud rate to 230400.
Added uart signals to debugger.
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2022-04-17 15:23:39 -05:00 |
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David Harris
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b4902a6ff9
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First implementation of WFI timeout wait
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2022-04-17 17:20:35 +00:00 |
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David Harris
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6769f0cb43
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Added comments in fcvt
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2022-04-17 16:53:10 +00:00 |
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David Harris
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d71940d96d
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Simplified SLT logic
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2022-04-17 16:49:51 +00:00 |
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Ross Thompson
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55c667b60d
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Commented output power analysis to speed simulation.
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2022-04-16 15:32:59 -05:00 |
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Ross Thompson
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f8bdb6db49
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-16 14:59:03 -05:00 |
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Ross Thompson
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bfc68bef69
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Fixed possible bugs in LRSC.
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2022-04-16 14:45:31 -05:00 |
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David Harris
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0932d4df46
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Added WFI support to IFU to keep it in the pipeline
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2022-04-14 17:26:17 +00:00 |
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David Harris
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c3bca40e05
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Added WFI to the testbench instruction name decoder
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2022-04-14 17:12:11 +00:00 |
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David Harris
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6e16922aae
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WFI should set EPC to PC+4
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2022-04-14 17:05:22 +00:00 |
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bbracker
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0e183be3e5
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fix testbench timing bug where interrupt forcing didn't happen soon enough because it was waiting on StallM
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2022-04-14 09:23:21 -07:00 |
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bbracker
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489ce4269a
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fix ReadDataM forcing
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2022-04-13 15:32:00 -07:00 |
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Ross Thompson
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65573f07b7
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-13 13:39:47 -05:00 |
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bbracker
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c697c17b05
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-13 05:35:56 -07:00 |
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bbracker
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016e960401
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change interrupt spoofing to happen at negative clock edges
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2022-04-13 04:31:23 -07:00 |
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bbracker
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3465d8cd32
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improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS
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2022-04-13 03:37:53 -07:00 |
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bbracker
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67ef47b25b
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whoops forgot to update AttemptedInstructionCount in interrupt spoofing
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2022-04-13 00:49:37 -07:00 |
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bbracker
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6c3d274970
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change testbench-linux to by default use attempted instruction count for warning/error messages
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2022-04-12 21:22:08 -07:00 |
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Ross Thompson
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2eb2263e94
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-12 19:38:04 -05:00 |
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Ross Thompson
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adb4e30c45
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Missed the force on uart for no tracking.
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2022-04-12 19:37:44 -05:00 |
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Ross Thompson
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d087deef65
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-12 17:56:48 -05:00 |
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Ross Thompson
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22f2e88553
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UART and clock speed changes to support 30Mhz.
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2022-04-12 17:56:36 -05:00 |
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