Katherine Parry
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90d5fdba04
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FMV.X.D imperas test passes
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2021-05-24 14:44:30 -04:00 |
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Katherine Parry
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06af239e6c
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FMV.D.X imperas test passes
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2021-05-20 22:17:59 -04:00 |
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bbracker
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8a7fc959eb
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small synthesis fixes
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2021-05-04 15:21:01 -04:00 |
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Ross Thompson
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6e803b724e
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Merge branch 'tests' into icache-almost-working
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2021-04-25 21:25:36 -05:00 |
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James E. Stine
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cff08adc3a
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Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.
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2021-04-02 06:27:37 -05:00 |
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ushakya22
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6b9ae41302
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-03-30 15:25:07 -04:00 |
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Ross Thompson
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a99c0502e5
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Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions.
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2021-03-24 15:56:55 -05:00 |
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Shreya Sanghai
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eb86bfc084
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removed unnecesary PC registers in ifu
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2021-03-18 16:31:21 -04:00 |
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David Harris
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865c103599
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64-bit AMO debugged
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2021-03-11 23:18:33 -05:00 |
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David Harris
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42275e92ed
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Initial untested implementation of AMO instructions
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2021-03-11 00:11:31 -05:00 |
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David Harris
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17c0f9629a
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WALLY-LRSC atomic test passing
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2021-03-09 09:28:25 -05:00 |
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Ross Thompson
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66e84f3a2c
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Merge branch 'bp' into main
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
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2021-03-04 13:35:46 -06:00 |
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David Harris
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2543c29839
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Initial (untested) implementation of lr and sc
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2021-03-01 00:09:45 -05:00 |
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Ross Thompson
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7592a0dacb
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Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.
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2021-02-26 20:12:27 -06:00 |
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David Harris
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cf03afa880
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Eliminated flushing pipeline on CSR reads
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2021-02-26 17:00:07 -05:00 |
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David Harris
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015b632eb1
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Cleaned out unused signals
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2021-02-26 09:17:36 -05:00 |
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David Harris
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a16fd95eed
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Restored to working multiplier after Lab 2
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2021-02-25 15:32:43 -05:00 |
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David Harris
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d00d42cf9a
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Merged bus into main
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2021-02-25 00:28:41 -05:00 |
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David Harris
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64536dbc34
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Removed multiplier for lab 2
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2021-02-17 16:06:16 -05:00 |
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David Harris
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cb0054b524
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Multiply instructions working
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2021-02-17 15:29:20 -05:00 |
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David Harris
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8dec69c2ce
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Added MUL
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2021-02-15 22:27:35 -05:00 |
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David Harris
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3551cc859b
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Data memory bus integration
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2021-02-07 23:21:55 -05:00 |
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David Harris
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91f6858de7
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-02-02 19:44:43 -05:00 |
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David Harris
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a44c2abb12
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Minor tweaks
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2021-02-02 19:44:37 -05:00 |
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Noah Boorstin
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00d9e13d68
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same thing but do that right this time
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2021-02-02 21:47:15 +00:00 |
|
Noah Boorstin
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56ff32f857
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change undefined syntax in extend.sv
don't need verilator execption anymore
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2021-02-02 21:39:20 +00:00 |
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David Harris
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d56d7a75a6
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Rename ifu/dmem/ebu signals to match uarch diagram
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2021-02-02 15:09:24 -05:00 |
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David Harris
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4fbb5f0f1b
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Cleaned up hazard interface
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2021-02-02 13:53:13 -05:00 |
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David Harris
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c23afbda3a
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Moved LoadStall generation to IEU
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2021-02-02 13:42:23 -05:00 |
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David Harris
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aad1d3d7dd
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Moved writeback pipeline registers from datapth into DMEM and CSR
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2021-02-02 13:02:31 -05:00 |
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David Harris
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9d7e242596
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Moved fpu to temporary location to fix compile and cleaned up interface formatting
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2021-02-01 23:44:41 -05:00 |
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David Harris
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396cea1ea7
|
Reorganized src hierarchically
|
2021-01-30 11:50:37 -05:00 |
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