David Harris
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d7be94fab2
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Cleaned up SelBusWord
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2022-08-25 11:18:13 -07:00 |
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David Harris
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7a129af9ad
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Removed M sufix from busdp signals
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2022-08-25 11:13:01 -07:00 |
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David Harris
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84ba62a04c
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Renamed LSUFunct3M to Funct3 in busdp
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2022-08-25 11:08:12 -07:00 |
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David Harris
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78618f5fc0
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Renaming LSU signals from busdp
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2022-08-25 11:05:10 -07:00 |
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David Harris
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cd02c894df
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renamed BusBuffer to FetchBuffer
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2022-08-25 10:44:39 -07:00 |
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David Harris
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5dc4fb757a
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Continued busdp/ebu simplification
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2022-08-25 10:20:02 -07:00 |
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David Harris
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24ce72f0a2
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-25 09:52:49 -07:00 |
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David Harris
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89860588b8
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Renamed AHB signals coming out of LSU to LSH_<AHBNAME>
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2022-08-25 09:52:08 -07:00 |
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Ross Thompson
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bd9401179d
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BROKEN. Don't use this commit.
Issue running cacheless with bus.
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2022-08-25 11:02:46 -05:00 |
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Ross Thompson
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5cc4f1f1cd
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Added generate around uncore.
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2022-08-25 10:35:24 -05:00 |
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Ross Thompson
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1e1646da90
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Added generate around ebu.
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2022-08-25 09:24:13 -05:00 |
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Ross Thompson
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72b886ec8f
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-25 09:03:34 -05:00 |
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Ross Thompson
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bc0edc7bdf
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Updated ila signals.
Improve fpga wave config.
added back in the fpga preload.
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2022-08-25 09:03:29 -05:00 |
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David Harris
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4ecdbb308a
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Renamed DCache to Cache in busdp/busfsm signal interface
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2022-08-25 06:21:22 -07:00 |
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David Harris
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b9dc8d9e33
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Cleanup typos
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2022-08-25 04:32:19 -07:00 |
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David Harris
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cb2c0fe027
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Minor name cleanups
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2022-08-25 04:28:25 -07:00 |
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David Harris
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a3828420c0
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Replaced dtim with rom-based IROM in IFU. Moved cache control signals out of DTIM and IROM
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2022-08-25 04:06:27 -07:00 |
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David Harris
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fe3147806d
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removed simpleram and modified dtim to use bram1p1rw
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2022-08-25 03:39:57 -07:00 |
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David Harris
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b3a13a01f8
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Stripped write capaibilty out of rom_ahb
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2022-08-24 17:23:08 -07:00 |
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David Harris
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e6077f1f16
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Added ROM module and moved memories into generic/mem
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2022-08-24 17:03:22 -07:00 |
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David Harris
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1ef0c7c2be
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-24 16:30:28 -07:00 |
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David Harris
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9d5468887e
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Ram cleanup
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2022-08-24 16:30:25 -07:00 |
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Ross Thompson
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22e989ac7b
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No longer need wally-pipelined-fpga.do.
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2022-08-24 18:10:45 -05:00 |
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Ross Thompson
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b650d7e05a
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Renamed RAM to UNCORE_RAM.
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2022-08-24 18:09:07 -05:00 |
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Ross Thompson
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c636387613
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Merged testbench-fpga into testbench.
Modified SDC to simplify LimitTimers. LimitTimers needs to be 0 for implmementation and 1 for simulation.
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2022-08-24 17:52:25 -05:00 |
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Ross Thompson
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07b2858890
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added SD card and external ram to common testbench.
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2022-08-24 13:27:18 -05:00 |
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Ross Thompson
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012559169b
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Fixed lint errors with bram wrapper.
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2022-08-24 13:19:23 -05:00 |
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Ross Thompson
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c6927d2ace
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Modified the lsu/ifu memory configurations.
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2022-08-24 12:35:15 -05:00 |
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David Harris
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e2138d8d0f
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bram synthesis test
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2022-08-23 19:34:45 -07:00 |
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David Harris
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b8cc06a434
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-08-24 00:09:20 +00:00 |
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David Harris
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a1311c06ef
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Rolled back synth scripts to fff91ae commit before Madeleine's modifications to write config files; the modified version is failing right away with trouble copying configs
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2022-08-24 00:09:16 +00:00 |
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Ross Thompson
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31d0ad4e38
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-23 18:57:43 -05:00 |
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Ross Thompson
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0c52c7f69c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-23 18:52:15 -05:00 |
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Ross Thompson
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ee3d968da0
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Found small bug in busfsm which was issuing 1 extra memory read after each cache line fetch. Does not appear to have translated to an extra read out of ahblite.
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2022-08-23 18:51:11 -05:00 |
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David Harris
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8d48ff4e63
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Fixed FPU-IEU forwarding stall
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2022-08-23 14:14:41 -07:00 |
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David Harris
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8b2e368805
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Only stall FPU to IEU on convert instructions with dependencies
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2022-08-23 12:57:18 -07:00 |
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David Harris
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113258a0d0
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Cleaned up fcvt selection control to IEU and FPUIllegalInst signals
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2022-08-23 12:17:19 -07:00 |
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David Harris
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69be6d0873
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Simplify IEU-FP datapath
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2022-08-23 11:16:36 -07:00 |
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David Harris
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746842107b
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Improved illegal instruction checking in FPU
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2022-08-23 11:08:02 -07:00 |
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David Harris
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27cca2e3fd
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Fixed LSU typos
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2022-08-23 10:23:08 -07:00 |
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David Harris
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46f30d3dbe
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-23 10:14:59 -07:00 |
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David Harris
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13831aa3d3
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typo in srtfsm
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2022-08-23 10:14:54 -07:00 |
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Katherine Parry
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f9aa94f87b
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-08-23 16:36:32 +00:00 |
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Katherine Parry
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72a54ef621
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renamed rounding bits to L,G,R,S and fixed lint warning
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2022-08-23 16:36:20 +00:00 |
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Ross Thompson
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1f74528792
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-23 11:15:04 -05:00 |
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Ross Thompson
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7080fe7788
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Reversed order of supported sized in adrdecs.
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2022-08-23 11:14:53 -05:00 |
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Ross Thompson
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b0606a1699
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Replaced FPU data replicaiton on WriteData bus with 0 extention.
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2022-08-23 10:46:03 -05:00 |
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Ross Thompson
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b9fadc11c3
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Replaced LSU data replication with 0 extention.
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2022-08-23 10:43:47 -05:00 |
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Ross Thompson
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cd0da2e3b3
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Updated the names of the *WriteDataM inside the LSU to more meaningful names.
Moved the FWriteDataMux so that the bus and dtim both get fpu stores.
Modified the PMA to disallow double sized reads when XLEN=32.
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2022-08-23 10:34:39 -05:00 |
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David Harris
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9e3d13ca52
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Q depends on D
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2022-08-23 08:29:59 -07:00 |
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