Merge branch 'main' of github.com:davidharrishmc/riscv-wally into boot

bin/parseHPMC.py

@@ -91,13 +91,24 @@ def ProcessFile(fileName):
             HPMClist = { }
         elif(len(lineToken) > 4 and lineToken[1][0:3] == 'Cnt'):
             countToken = line.split('=')[1].split()
-            value = countToken[0]
+            value = int(countToken[0])
             name = ' '.join(countToken[1:])
             HPMClist[name] = value
         elif ('is done' in line):
             benchmarks.append((testName, opt, HPMClist))
     return benchmarks
 
+def ComputeAverage(benchmarks):
+    average = {}
+    for (testName, opt, HPMClist) in benchmarks:
+        for field in HPMClist:
+            value = HPMClist[field]
+            if field not in average:
+                average[field] = value
+            else:
+                average[field] += value
+    benchmarks.append(('All', '', average))
+
 def FormatToPlot(currBenchmark):
     names = []
     values = []
@@ -111,6 +122,7 @@ if(sys.argv[1] == '-b'):
     configList = []
     for config in sys.argv[2::]:
         benchmarks = ProcessFile(config)
+        ComputeAverage(benchmarks)
         ComputeAll(benchmarks)
         configList.append((config.split('.')[0], benchmarks))
 
@@ -152,6 +164,7 @@ if(sys.argv[1] == '-b'):
 else:
     # steps 1 and 2
     benchmarks = ProcessFile(sys.argv[1])
+    ComputeAverage(benchmarks)
     # 3 process into useful data
     # cache hit rates
     # cache fill time

pipelined/config/shared/wally-constants.vh

@@ -123,19 +123,24 @@
 `define CVTLEN ((`NF<`XLEN) ? (`XLEN) : (`NF))
 `define LLEN ((`FLEN<`XLEN) ? (`XLEN) : (`FLEN))
 `define LOGCVTLEN $unsigned($clog2(`CVTLEN+1))
-`define NORMSHIFTSZ ((`QLEN+`NF+1) > (3*`NF+6) ? (`QLEN+`NF+1) : (3*`NF+6))
+`define NORMSHIFTSZ (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVb + 1 +`NF+1) > (3*`NF+6) ? (`DIVb + 1 +`NF+1) : (3*`NF+6)))
 `define LOGNORMSHIFTSZ ($clog2(`NORMSHIFTSZ))
-`define CORRSHIFTSZ ((`DIVRESLEN+`NF) > (3*`NF+6) ? (`DIVRESLEN+`NF) : (3*`NF+4))
+`define CORRSHIFTSZ (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVN+1+`NF) > (3*`NF+4) ? (`DIVN+1+`NF) : (3*`NF+4)))
 
 // division constants
-`define DIVN        (`NF<`XLEN ? `XLEN : `NF+3) // standard length of input
+
-`define DIVRESLEN   (`NF<`XLEN ? `XLEN : `NF+4) // result length for postprocessing
+`define DIVN        (((`NF<`XLEN) & `IDIV_ON_FPU) ? `XLEN : `NF+2) // standard length of input
-`define LOGR        (`RADIX==2 ? 32'h1 : 32'h2) // r = log(R)
+`define LOGR        ($clog2(`RADIX))            // r = log(R)
 `define RK          (`LOGR*`DIVCOPIES)          // r*k used for intdiv preproc
 `define LOGRK       ($clog2(`RK))               // log2(r*k)
 `define FPDUR       ((`DIVN+1+(`LOGR*`DIVCOPIES))/(`LOGR*`DIVCOPIES)+(`RADIX/4))
 `define DURLEN      ($clog2(`FPDUR+1))
-`define QLEN        (`FPDUR*`LOGR*`DIVCOPIES)
+`define DIVb        (`FPDUR*`LOGR*`DIVCOPIES-1) // canonical fdiv size (b)
-`define DIVb        (`FPDUR*`LOGR*`DIVCOPIES-1) // canonical fdiv size
 `define DIVBLEN     ($clog2(`DIVb+1)-1)
 `define DIVa        (`DIVb+1-`XLEN)             // used for idiv on fpu
+
+// Disable spurious Verilator warnings
+
+/* verilator lint_off STMTDLY */
+/* verilator lint_off ASSIGNDLY */
+/* verilator lint_off PINCONNECTEMPTY */

pipelined/config/shared/wally-shared.vh

@@ -23,8 +23,8 @@
 ///////////////////////////////////////////
 
 // division constants
-`define RADIX       32'h4
+`define RADIX 32'h4
-`define DIVCOPIES   32'h2
+`define DIVCOPIES 32'h4
 
 // Memory synthesis configuration
 `define USE_SRAM 0
@@ -32,8 +32,3 @@
 // shared constants
 `include "wally-constants.vh"
 
-// Disable spurious Verilator warnings
-
-/* verilator lint_off STMTDLY */
-/* verilator lint_off ASSIGNDLY */
-/* verilator lint_off PINCONNECTEMPTY */

pipelined/src/cache/cache.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Storage for data and meta data.
 //
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 //
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/cache/cacheLRU.sv

@@ -6,26 +6,22 @@
 //          Tested for Powers of 2.
 //
 //
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/cache/cachefsm.sv

@@ -6,26 +6,22 @@
 //
 // Purpose: Controller for the dcache fsm
 //
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/cache/cacheway.sv

@@ -6,26 +6,22 @@
 //
 // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/cache/subcachelineread.sv

@@ -6,26 +6,22 @@
 //
 // Purpose: Controller for the dcache fsm
 //
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/ebu/ahbcacheinterface.sv

@@ -10,26 +10,22 @@
 // This register should be necessary for timing.  There is no register in the uncore or
 // ahblite controller between the memories and this cache.
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/ebu/ahbinterface.sv

@@ -10,26 +10,22 @@
 // This register should be necessary for timing.  There is no register in the uncore or
 // ahblite controller between the memories and this cache.
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/ebu/amoalu.sv

@@ -6,26 +6,22 @@
 //
 // Purpose: Performs AMO operations
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/ebu/buscachefsm.sv

@@ -6,26 +6,22 @@
 //
 // Purpose: Load/Store Unit's interface to BUS for cacheless system
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/ebu/busfsm.sv

@@ -6,26 +6,22 @@
 //
 // Purpose: Load/Store Unit's interface to BUS for cacheless system
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/ebu/controllerinputstage.sv

@@ -12,26 +12,22 @@
 //          Bus width presently matches XLEN
 //          Anticipate replacing this with an AXI bus interface to communicate with FPGA DRAM/Flash controllers
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/ebu/ebu.sv

@@ -12,26 +12,22 @@
 //          Bus width presently matches XLEN
 //          Anticipate replacing this with an AXI bus interface to communicate with FPGA DRAM/Flash controllers
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/fpu/fclassify.sv

@@ -4,44 +4,42 @@
 // Written: me@KatherineParry.com
 // Modified: 7/5/2022
 //
-// Purpose: classify unit
+// Purpose: Floating-point classify unit
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 `include "wally-config.vh"
 
 module fclassify (
-    input logic         Xs,     // sign bit
+    input  logic                Xs,         // sign bit
-    input logic         XNaN,   // is NaN
+    input  logic                XNaN,       // is NaN
-    input logic         XSNaN,  // is signaling NaN
+    input  logic                XSNaN,      // is signaling NaN
-    input logic         XSubnorm,// is Subnormal
+    input  logic                XSubnorm,   // is Subnormal
-    input logic         XZero,  // is zero
+    input  logic                XZero,      // is zero
-    input logic         XInf,   // is infinity
+    input  logic                XInf,       // is infinity
-    output logic [`XLEN-1:0] ClassRes// classify result
+    output logic [`XLEN-1:0]    ClassRes    // classify result
 );
 
-    logic PInf, PZero, PNorm, PSubnorm;
+    logic PInf, PZero, PNorm, PSubnorm; // is the input a positive infinity/zero/normal/subnormal
-    logic NInf, NZero, NNorm, NSubnorm;
+    logic NInf, NZero, NNorm, NSubnorm; // is the input a negitive infinity/zero/normal/subnormal
-    logic XNorm;
+    logic XNorm;                        // is the input normal
    
     // determine the sub categories
     assign XNorm= ~(XNaN | XInf| XSubnorm| XZero);

pipelined/src/fpu/fcmp.sv

@@ -5,28 +5,26 @@
 // Written: me@KatherineParry.com
 // Modified: 7/5/2022
 //
-// Purpose: Comparison unit
+// Purpose: Floating-point comparison unit
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
@@ -39,18 +37,18 @@
 //    011   less than or equal
 
 module fcmp (   
-   input logic  [`FMTBITS-1:0]   Fmt,      // format of fp number
+   input  logic [`FMTBITS-1:0]   Fmt,           // format of fp number
-   input logic  [2:0]            OpCtrl,   // see above table
+   input  logic [2:0]            OpCtrl,        // see above table
-   input logic                   Xs, Ys,   // input signs
+   input  logic                  Xs, Ys,        // input signs
-   input logic  [`NE-1:0]        Xe, Ye,   // input exponents
+   input  logic [`NE-1:0]        Xe, Ye,        // input exponents
-   input logic  [`NF:0]          Xm, Ym,   // input mantissa
+   input  logic [`NF:0]          Xm, Ym,        // input mantissa
-   input logic                   XZero, YZero, // is zero
+   input  logic                  XZero, YZero,  // is zero
-   input logic                   XNaN, YNaN,   // is NaN
+   input  logic                  XNaN, YNaN,    // is NaN
-   input logic                   XSNaN, YSNaN, // is signaling NaN
+   input  logic                  XSNaN, YSNaN,  // is signaling NaN
-   input logic  [`FLEN-1:0]      X, Y,       // original inputs (before unpacker)
+   input  logic [`FLEN-1:0]      X, Y,          // original inputs (before unpacker)
-   output logic                  CmpNV,      // invalid flag
+   output logic                  CmpNV,         // invalid flag
-   output logic [`FLEN-1:0]      CmpFpRes,   // compare floating-point result
+   output logic [`FLEN-1:0]      CmpFpRes,      // compare floating-point result
-   output logic [`XLEN-1:0]      CmpIntRes   // compare integer result
+   output logic [`XLEN-1:0]      CmpIntRes      // compare integer result
    );
 
    logic LTabs, LT, EQ;         // is X < or > or = Y

pipelined/src/fpu/fctrl.sv

@@ -4,81 +4,90 @@
 // Written: me@KatherineParry.com
 // Modified: 7/5/2022
 //
-// Purpose: control unit
+// Purpose: floating-point control unit
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 `include "wally-config.vh"
 
 module fctrl (
-  input  logic       clk,
+  input  logic                clk,
-  input  logic       reset,
+  input  logic                reset,
-  input  logic       StallE, StallM, StallW, // stall signals
+  // input control signals
-  input  logic       FlushE, FlushM, FlushW, // flush signals
+  input  logic                StallE, StallM, StallW, // stall signals
-  input  logic [31:0] InstrD,
+  input  logic                FlushE, FlushM, FlushW, // flush signals
-  input  logic [6:0] Funct7D,   // bits 31:25 of instruction - may contain percision
+  input  logic                IntDivE,                // is inteteger division
-  input  logic [6:0] OpD,       // bits 6:0 of instruction
+  input  logic [2:0]          FRM_REGW,               // rounding mode from CSR
-  input  logic [4:0] Rs2D,      // bits 24:20 of instruction
+  input  logic [1:0]          STATUS_FS,              // is FPU enabled?
-  input  logic [2:0] Funct3D, Funct3E,   // bits 14:12 of instruction - may contain rounding mode
+  input  logic                FDivBusyE,              // is the divider busy
-  input  logic       MDUE,
+  // intruction
-  input  logic [2:0] FRM_REGW,  // rounding mode from CSR
+  input  logic [31:0]         InstrD,                 // the full instruction
-  input  logic [1:0] STATUS_FS, // is FPU enabled?
+  input  logic [6:0]          Funct7D,                // bits 31:25 of instruction - may contain percision
-  input  logic       FDivBusyE,  // is the divider busy
+  input  logic [6:0]          OpD,                    // bits 6:0 of instruction
-  output logic       IllegalFPUInstrM, // Is the instruction an illegal fpu instruction
+  input  logic [4:0]          Rs2D,                   // bits 24:20 of instruction
-  output logic 		         FRegWriteE, FRegWriteM, FRegWriteW, // FP register write enable
+  input  logic [2:0]          Funct3D, Funct3E,       // bits 14:12 of instruction - may contain rounding mode
-  output logic [2:0] 	      FrmM,                   // FP rounding mode
+  // input mux selections
+  output logic                XEnD, YEnD, ZEnD,       // enable inputs
+  output logic                XEnE, YEnE, ZEnE,       // enable inputs
+  // opperation mux selections
+  output logic 		            FCvtIntE, FCvtIntW,     // convert to integer opperation
+  output logic [2:0] 	        FrmM,                   // FP rounding mode
   output logic [`FMTBITS-1:0] FmtE, FmtM,             // FP format
-  output logic 		         FDivStartE, IDivStartE,             // Start division or squareroot
+  output logic [2:0] 	        OpCtrlE, OpCtrlM,       // Select which opperation to do in each component
-  output logic              XEnD, YEnD, ZEnD,
+  output logic                FpLoadStoreM,           // FP load or store instruction
-  output logic              XEnE, YEnE, ZEnE,
+  output logic [1:0] 	        PostProcSelE, PostProcSelM,         // select result in the post processing unit
-  output logic 		         FWriteIntE, FCvtIntE, FWriteIntM,                         // Write to integer register
+  output logic [1:0] 	        FResSelE, FResSelM, FResSelW,       // Select one of the results that finish in the memory stage
-  output logic [2:0] 	      OpCtrlE, OpCtrlM,       // Select which opperation to do in each component
+  // register control signals
-  output logic [1:0] 	      FResSelE, FResSelM, FResSelW,       // Select one of the results that finish in the memory stage
+  output logic 		            FRegWriteE, FRegWriteM, FRegWriteW, // FP register write enable
-  output logic [1:0] 	      PostProcSelE, PostProcSelM, // select result in the post processing unit
+  output logic 		            FWriteIntE, FWriteIntM,             // Write to integer register
-  output logic              FCvtIntW,
+  output logic [4:0] 	        Adr1D, Adr2D, Adr3D,                // adresses of each input
-  output logic [4:0] 	      Adr1D, Adr2D, Adr3D,                // adresses of each input
+  output logic [4:0] 	        Adr1E, Adr2E, Adr3E,                // adresses of each input
-  output logic [4:0] 	      Adr1E, Adr2E, Adr3E                // adresses of each input
+  // other control signals
+  output logic                IllegalFPUInstrM,                   // Is the instruction an illegal fpu instruction
+  output logic 		            FDivStartE, IDivStartE              // Start division or squareroot
   );
 
   `define FCTRLW 12
-  logic [`FCTRLW-1:0] ControlsD;
+
-  logic       IllegalFPUInstrD, IllegalFPUInstrE;
+  logic [`FCTRLW-1:0]   ControlsD;    // control signals
-  logic 		  FRegWriteD; // FP register write enable
+  logic                 IllegalFPUInstrD, IllegalFPUInstrE; // is the intruction an illegal fpu instruction
-  logic 		  FDivStartD; // integer register write enable
+  logic 		            FRegWriteD;   // FP register write enable
-  logic 		  FWriteIntD; // integer register write enable
+  logic 		            FDivStartD;   // start division/sqrt
-  logic [2:0] 	      OpCtrlD;       // Select which opperation to do in each component
+  logic 		            FWriteIntD;   // integer register write enable
-  logic [1:0] 	      PostProcSelD; // select result in the post processing unit
+  logic [2:0] 	        OpCtrlD;      // Select which opperation to do in each component
-  logic [1:0] 	      FResSelD;       // Select one of the results that finish in the memory stage
+  logic [1:0] 	        PostProcSelD; // select result in the post processing unit
-  logic [2:0] FrmD, FrmE;                   // FP rounding mode
+  logic [1:0] 	        FResSelD;     // Select one of the results that finish in the memory stage
-  logic [`FMTBITS-1:0] FmtD;             // FP format
+  logic [2:0]           FrmD, FrmE;   // FP rounding mode
-  logic [1:0] Fmt;
+  logic [`FMTBITS-1:0]  FmtD;         // FP format
-  logic       SupportedFmt;
+  logic [1:0]           Fmt;          // format - before possible reduction
-  logic       FCvtIntD, FCvtIntM;
+  logic                 SupportedFmt; // is the format supported
+  logic                 FCvtIntD, FCvtIntM; // convert to integer opperation
 
   // FPU Instruction Decoder
   assign Fmt = Funct7D[1:0];
+
   // Note: only Fmt is checked; fcvt does not check destination format
   assign SupportedFmt = (Fmt == 2'b00 | (Fmt == 2'b01 & `D_SUPPORTED) |
                          (Fmt == 2'b10 & `ZFH_SUPPORTED) | (Fmt == 2'b11 & `Q_SUPPORTED));
+
+  // decode the instruction                       
   always_comb
     if (STATUS_FS == 2'b00) // FPU instructions are illegal when FPU is disabled
       ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0;
@@ -183,8 +192,10 @@ module fctrl (
   assign FrmD = &Funct3D ? FRM_REGW : Funct3D;
 
   // Precision
-  //    0-single
+  //    00 - single
-  //    1-double
+  //    01 - double
+  //    10 - half
+  //    11 - quad
   
     if (`FPSIZES == 1)
       assign FmtD = 0;
@@ -213,56 +224,57 @@ module fctrl (
   assign ZEnD = (PostProcSelD==2'b10)&(FResSelD==2'b01)&(~OpCtrlD[2]|OpCtrlD[1]);                  // fma, add, sub
   
 
-//  Final Res Sel:
+  //  Final Res Sel:
-//        fp      int
+  //        fp      int
-//  00  other     cmp
+  //  00  other     cmp
-//  01  postproc  cvt
+  //  01  postproc  cvt
-//  10  store     class
+  //  10  store     class
-//  11            mv
+  //  11            mv
 
-//  post processing Sel:
+  //  post processing Sel:
-//  00  cvt
+  //  00  cvt
-//  01  div
+  //  01  div
-//  10  fma
+  //  10  fma
 
-//  Other Sel:
+  //  Other Sel:
-//    Ctrl signal = {OpCtrl[2], &FOpctrl[1:0]}
+  //    Ctrl signal = {OpCtrl[2], &FOpctrl[1:0]}
-//        000 - sign            00
+  //        000 - sign            00
-//        001 - negate sign     00
+  //        001 - negate sign     00
-//        010 - xor sign        00
+  //        010 - xor sign        00
-//        011 - mv to fp        01
+  //        011 - mv to fp        01
-//        110 - min             10
+  //        110 - min             10
-//        101 - max             10
+  //        101 - max             10
 
-//  OpCtrl:
+  //  OpCtrl:
-//    Fma: {not multiply-add?, negate prod?, negate Z?}
+  //    Fma: {not multiply-add?, negate prod?, negate Z?}
-//        000 - fmadd
+  //        000 - fmadd
-//        001 - fmsub
+  //        001 - fmsub
-//        010 - fnmsub
+  //        010 - fnmsub
-//        011 - fnmadd
+  //        011 - fnmadd
-//        100 - mul
+  //        100 - mul
-//        110 - add
+  //        110 - add
-//        111 - sub
+  //        111 - sub
-//    Div: 
+  //    Div: 
-//        0 - div
+  //        0 - div
-//        1 - sqrt
+  //        1 - sqrt
-//    Cvt Int: {Int to Fp?, 64 bit int?, signed int?}
+  //    Cvt Int: {Int to Fp?, 64 bit int?, signed int?}
-//    Cvt Fp: output format
+  //    Cvt Fp: output format
-//        10 - to half
+  //        10 - to half
-//        00 - to single
+  //        00 - to single
-//        01 - to double
+  //        01 - to double
-//        11 - to quad
+  //        11 - to quad
-//    Cmp: {equal?, less than?}
+  //    Cmp: {equal?, less than?}
-//        010 - eq
+  //        010 - eq
-//        001 - lt
+  //        001 - lt
-//        011 - le
+  //        011 - le
-//        110 - min
+  //        110 - min
-//        101 - max
+  //        101 - max
-//    Sgn:
+  //    Sgn:
-//        00 - sign
+  //        00 - sign
-//        01 - negate sign
+  //        01 - negate sign
-//        10 - xor sign
+  //        10 - xor sign
 
+  // rename input adresses for readability
   assign Adr1D = InstrD[19:15];
   assign Adr2D = InstrD[24:20];
   assign Adr3D = InstrD[31:27];
@@ -274,15 +286,19 @@ module fctrl (
   flopenrc #(15) DEAdrReg(clk, reset, FlushE, ~StallE, {Adr1D, Adr2D, Adr3D}, {Adr1E, Adr2E, Adr3E});
   flopenrc #(1) DEFDivStartReg(clk, reset, FlushE, ~StallE|FDivBusyE, FDivStartD, FDivStartE);
   flopenrc #(3) DEEnReg(clk, reset, FlushE, ~StallE, {XEnD, YEnD, ZEnD}, {XEnE, YEnE, ZEnE});
-  if (`M_SUPPORTED) assign IDivStartE = MDUE & Funct3E[2];
-  else              assign IDivStartE = 0; 
 
-  //assign FCvtIntE = (FResSelE == 2'b01);
+  // Integer division on FPU divider
+  if (`M_SUPPORTED & `IDIV_ON_FPU) assign IDivStartE = IntDivE;
+  else                             assign IDivStartE = 0; 
 
   // E/M pipleine register
   flopenrc #(14+int'(`FMTBITS)) EMCtrlReg (clk, reset, FlushM, ~StallM,
               {FRegWriteE, FResSelE, PostProcSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, IllegalFPUInstrE, FCvtIntE},
               {FRegWriteM, FResSelM, PostProcSelM, FrmM, FmtM, OpCtrlM, FWriteIntM, IllegalFPUInstrM, FCvtIntM});
+  
+  // renameing for readability
+  assign FpLoadStoreM = FResSelM[1];
+
   // M/W pipleine register
   flopenrc #(4)  MWCtrlReg(clk, reset, FlushW, ~StallW,
           {FRegWriteM, FResSelM, FCvtIntM},

pipelined/src/fpu/fcvt.sv

@@ -7,42 +7,40 @@
 //
 // Purpose: Floating point conversions of configurable size
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // Int component of the Wally configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR Int PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
 
 module fcvt (
-    input logic                     Xs,         // input's sign
+    input  logic                    Xs,         // input's sign
-    input logic [`NE-1:0]           Xe,         // input's exponent
+    input  logic [`NE-1:0]          Xe,         // input's exponent
-    input logic [`NF:0]             Xm,         // input's fraction
+    input  logic [`NF:0]            Xm,         // input's fraction
-    input logic [`XLEN-1:0]         Int,        // integer input - from IEU
+    input  logic [`XLEN-1:0]        Int,        // integer input - from IEU
-    input logic [2:0]               OpCtrl,     // choose which opperation (look below for values)
+    input  logic [2:0]              OpCtrl,     // choose which opperation (look below for values)
-    input logic                     ToInt,      // is fp->int (since it's writting to the integer register)
+    input  logic                    ToInt,      // is fp->int (since it's writting to the integer register)
-    input logic                     XZero,      // is the input zero
+    input  logic                    XZero,      // is the input zero
-    input logic [`FMTBITS-1:0]      Fmt,        // the input's precision (11=quad 01=double 00=single 10=half)
+    input  logic [`FMTBITS-1:0]     Fmt,        // the input's precision (11=quad 01=double 00=single 10=half)
     output logic [`NE:0]            Ce,         // the calculated expoent
 	output logic [`LOGCVTLEN-1:0]   ShiftAmt,   // how much to shift by
-    output logic                    ResSubnormUf, // does the result underflow or is Subnormalized
+    output logic                    ResSubnormUf,// does the result underflow or is subnormal
     output logic                    Cs,         // the result's sign
     output logic                    IntZero,    // is the integer zero?
     output logic [`CVTLEN-1:0]      LzcIn       // input to the Leading Zero Counter (priority encoder)
@@ -105,6 +103,8 @@ module fcvt (
     //             fp  -> fp : | fraction         | 00000... (if needed) | 
     assign LzcInFull = IntToFp ? {TrimInt, {`CVTLEN-`XLEN+1{1'b0}}} :
                              {Xm, {`CVTLEN-`NF{1'b0}}};
+
+    // used as shifter input in postprocessor
     assign LzcIn = LzcInFull[`CVTLEN-1:0];
     
     lzc #(`CVTLEN+1) lzc (.num(LzcInFull), .ZeroCnt(LeadingZeros));
@@ -113,16 +113,6 @@ module fcvt (
     // exp calculations
     ///////////////////////////////////////////////////////////////////////////
 
-
-    // *** possible optimizaations:
-        //  - if subtracting exp by bias only the msb needs a full adder, the rest can be HA - dunno how to implement this for synth
-        //  - Smaller exp -> Larger Exp can be calculated with: *** can use in Other units??? FMA??? insert this thing in later
-        //          Exp if in range: {~Exp[SNE-1], Exp[SNE-2:0]}
-        //          Exp in range if: Exp[SNE-1] = 1 & Exp[LNE-2:SNE] = 1111... & Exp[LNE-1] = 0 | Exp[SNE-1] = 0 & Exp[LNE-2:SNE] = 000... & Exp[LNE-1] = 1
-        //                     i.e.: &Exp[LNE-2:SNE-1] xor Exp[LNE-1]
-        //          Too big if:      Exp[LNE-1] = 1
-        //          Too small if:    none of the above
-
     // Select the bias of the output
     //      fp -> int : select 1
     //      ??? -> fp : pick the new bias depending on the output format 
@@ -156,6 +146,8 @@ module fcvt (
             endcase
         assign NewBias = ToInt ? (`NE-1)'(1) : NewBiasToFp; 
     end
+
+
     // select the old exponent
     //      int -> fp : largest bias + XLEN-1
     //      fp -> ??? : XExp
@@ -164,7 +156,7 @@ module fcvt (
     // calculate CalcExp
     //      fp -> fp : 
     //          - XExp - Largest bias + new bias - (LeadingZeros+1)
-    //                                          only do ^ if the input was Subnormalized
+    //                                          only do ^ if the input was subnormal
     //              - convert the expoenent to the final preciaion (Exp - oldBias + newBias)
     //              - correct the expoent when there is a normalization shift ( + LeadingZeros+1) 
     //              - the plus 1 is built into the leading zeros by counting the leading zeroes in the mantissa rather than the fraction
@@ -182,7 +174,7 @@ module fcvt (
     //                  |  0's |     Mantissa      |      0's if nessisary     |
     //                  |     keep        |
     //
-    //              - if the input is Subnormalized then we dont shift... so the  "- LeadingZeros" is just leftovers from other options
+    //              - if the input is subnormal then we dont shift... so the  "- LeadingZeros" is just leftovers from other options
     //      int -> fp : largest bias +  XLEN-1 - Largest bias + new bias - LeadingZeros = XLEN-1 + NewBias - LeadingZeros
     //              Process:
     //                      |XLEN|.0000
@@ -196,6 +188,8 @@ module fcvt (
     //
     //          oldexp         - biasold         - LeadingZeros                               + newbias
     assign Ce = {1'b0, OldExp} - (`NE+1)'(`BIAS) - {{`NE-`LOGCVTLEN+1{1'b0}}, (LeadingZeros)} + {2'b0, NewBias};
+
+
     // find if the result is dnormal or underflows
     //      - if Calculated expoenent is 0 or negitive (and the input/result is not exactaly 0)
     //      - can't underflow an integer to Fp conversion
@@ -211,17 +205,19 @@ module fcvt (
     //      fp -> int: 
     //          - shift left by CalcExp - essentially shifting until the unbiased exponent = 0
     //              - don't shift if supposed to shift right (underflowed or Subnorm input)
-    //      Subnormalized/undeflowed result fp -> fp:
+    //      subnormal/undeflowed result fp -> fp:
     //          - shift left by NF-1+CalcExp - to shift till the biased expoenent is 0
     //      ??? -> fp: 
     //          - shift left by LeadingZeros - to shift till the result is normalized
-    //              - only shift fp -> fp if the intital value is Subnormalized
+    //              - only shift fp -> fp if the intital value is subnormal
     //                  - this is a problem because the input to the lzc was the fraction rather than the mantissa
     //                  - rather have a few and-gates than an extra bit in the priority encoder??? *** is this true?
     always_comb
         if(ToInt)                       ShiftAmt = Ce[`LOGCVTLEN-1:0]&{`LOGCVTLEN{~Ce[`NE]}};
         else if (ResSubnormUf)  ShiftAmt = (`LOGCVTLEN)'(`NF-1)+Ce[`LOGCVTLEN-1:0];
         else                            ShiftAmt = LeadingZeros;
+
+        
     ///////////////////////////////////////////////////////////////////////////
     // sign
     ///////////////////////////////////////////////////////////////////////////

pipelined/src/fpu/fdivsqrt/fdivsqrt.sv

@@ -6,26 +6,24 @@
 //
 // Purpose: Combined Divide and Square Root Floating Point and Integer Unit
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
@@ -46,12 +44,12 @@ module fdivsqrt(
   input  logic SqrtE, SqrtM,
 	input  logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // these are the src outputs before the mux choosing between them and PCE to put in srcA/B
 	input  logic [2:0] 	Funct3E, Funct3M,
-	input  logic MDUE, W64E,
+	input  logic IntDivE, W64E,
-  output logic DivSM,
+  output logic DivStickyM,
   output logic FDivBusyE, IFDivStartE, FDivDoneE,
   output logic [`NE+1:0] QeM,
   output logic [`DIVb:0] QmM,
-  output logic [`XLEN-1:0] FPIntDivResultM
+  output logic [`XLEN-1:0] FIntDivResultM
 );
 
   // Floating-point division and square root module, with optional integer division and remainder
@@ -69,7 +67,7 @@ module fdivsqrt(
 
   // Integer div/rem signals
   logic BZeroM;                       // Denominator is zero
-  logic MDUM;                         // Integer operation
+  logic IntDivM;                         // Integer operation
   logic [`DIVBLEN:0] nE, nM, mM;      // Shift amounts
   logic NegQuotM, ALTBM, AsM, W64M;   // Special handling for postprocessor
   logic [`XLEN-1:0] AM;               // Original Numerator for postprocessor
@@ -80,16 +78,16 @@ module fdivsqrt(
     .Fmt(FmtE), .Sqrt(SqrtE), .XZeroE, .Funct3E, 
     .QeM, .X, .DPreproc, 
     // Int-specific 
-    .ForwardedSrcAE, .ForwardedSrcBE, .MDUE, .W64E, .ISpecialCaseE,
+    .ForwardedSrcAE, .ForwardedSrcBE, .IntDivE, .W64E, .ISpecialCaseE,
     .nE, .BZeroM, .nM, .mM, .AM, 
-    .MDUM, .W64M, .NegQuotM, .ALTBM, .AsM);
+    .IntDivM, .W64M, .NegQuotM, .ALTBM, .AsM);
 
   fdivsqrtfsm fdivsqrtfsm(                                // FSM
     .clk, .reset, .FmtE, .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, 
     .FDivStartE, .XsE, .SqrtE, .WZeroE, .FlushE, .StallM, 
     .FDivBusyE, .IFDivStartE, .FDivDoneE, .SpecialCaseM, 
     // Int-specific 
-    .IDivStartE, .ISpecialCaseE, .nE, .MDUE);
+    .IDivStartE, .ISpecialCaseE, .nE, .IntDivE);
 
   fdivsqrtiter fdivsqrtiter(                              // CSA Iterator
     .clk, .IFDivStartE, .FDivBusyE, .SqrtE, .X, .DPreproc, 
@@ -98,8 +96,8 @@ module fdivsqrt(
   fdivsqrtpostproc fdivsqrtpostproc(                      // Postprocessor
     .clk, .reset, .StallM, .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, 
     .SqrtE, .Firstun, .SqrtM, .SpecialCaseM, 
-    .QmM, .WZeroE, .DivSM, 
+    .QmM, .WZeroE, .DivStickyM, 
     // Int-specific 
     .nM, .mM, .ALTBM, .AsM, .BZeroM, .NegQuotM, .W64M, .RemOpM(Funct3M[1]), .AM, 
-    .FPIntDivResultM);
+    .FIntDivResultM);
 endmodule

pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv

@@ -4,28 +4,26 @@
 // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
 // Modified:13 January 2022
 //
-// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
+// Purpose: Exponent caclulation for divide and square root
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
@@ -70,7 +68,7 @@ module fdivsqrtexpcalc(
   assign SXExp = {2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, ell} - (`NE+2)'(`BIAS);
   assign SExp  = {SXExp[`NE+1], SXExp[`NE+1:1]} + {2'b0, Bias};
   
-  // correct exponent for Subnormalized input's normalization shifts
+  // correct exponent for subnormal input's normalization shifts
   assign DExp  = ({2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, ell} - {2'b0, Ye} + {{(`NE+1-`DIVBLEN){1'b0}}, m} + {3'b0, Bias}) & {`NE+2{~XZero}};
   assign Qe = Sqrt ? SExp : DExp;
 endmodule

pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv

@@ -6,26 +6,24 @@
 //
 // Purpose: Radix 2 F Addend Generator
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv

@@ -6,26 +6,24 @@
 //
 // Purpose: Radix 4 F Addend Generator
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv

@@ -4,28 +4,26 @@
 // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
 // Modified:13 January 2022
 //
-// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
+// Purpose: divsqrt state machine for multi-cycle operations
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
@@ -43,7 +41,7 @@ module fdivsqrtfsm(
   input  logic StallM,
   input  logic FlushE,
   input  logic WZeroE,
-  input  logic MDUE,
+  input  logic IntDivE,
   input  logic [`DIVBLEN:0] nE,
   input  logic ISpecialCaseE,
   output logic IFDivStartE,
@@ -65,7 +63,7 @@ module fdivsqrtfsm(
 
   // terminate immediately on special cases
   assign FSpecialCaseE = XZeroE | (YZeroE&~SqrtE) | XInfE | YInfE | XNaNE | YNaNE | (XsE&SqrtE);
-  if (`IDIV_ON_FPU) assign SpecialCaseE = MDUE ? ISpecialCaseE : FSpecialCaseE;
+  if (`IDIV_ON_FPU) assign SpecialCaseE = IntDivE ? ISpecialCaseE : FSpecialCaseE;
   else              assign SpecialCaseE = FSpecialCaseE;
   flopenr #(1) SpecialCaseReg(clk, reset, IFDivStartE, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc
 
@@ -103,7 +101,7 @@ module fdivsqrtfsm(
   always_comb begin 
     if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2
     else       fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
-    if (`IDIV_ON_FPU) cycles =  MDUE ? ((nE + 1)/`DIVCOPIES) : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
+    if (`IDIV_ON_FPU) cycles =  IntDivE ? ((nE + 1)/`DIVCOPIES) : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
     else              cycles = (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
   end 
 

pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv

@@ -4,28 +4,26 @@
 // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu 
 // Modified:13 January 2022
 //
-// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
+// Purpose: k stages of divsqrt logic, plus registers
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv

@@ -4,28 +4,26 @@
 // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
 // Modified:13 January 2022
 //
-// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
+// Purpose: Divide/Square root postprocessing
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
@@ -44,8 +42,8 @@ module fdivsqrtpostproc(
   input  logic [`DIVBLEN:0] nM, mM,
   output logic [`DIVb:0]    QmM, 
   output logic              WZeroE,
-  output logic              DivSM,
+  output logic              DivStickyM,
-  output logic [`XLEN-1:0]  FPIntDivResultM
+  output logic [`XLEN-1:0]  FIntDivResultM
 );
   
   logic [`DIVb+3:0] W, Sum, DM;
@@ -90,7 +88,7 @@ module fdivsqrtpostproc(
   //////////////////////////
 
   //  If the result is not exact, the sticky should be set
-  assign DivSM = ~WZeroM & ~(SpecialCaseM & SqrtM); // ***unsure why SpecialCaseM has to be gated by SqrtM, but otherwise fails regression on divide
+  assign DivStickyM = ~WZeroM & ~(SpecialCaseM & SqrtM); // ***unsure why SpecialCaseM has to be gated by SqrtM, but otherwise fails regression on divide
 
   // Determine if sticky bit is negative  // *** look for ways to optimize this.  Shift shouldn't be needed.
   assign Sum = WC + WS;
@@ -133,8 +131,8 @@ module fdivsqrtpostproc(
     if (`XLEN==64) begin
       mux2 #(64) resmux(IntDivResultM[`XLEN-1:0], 
         {{(`XLEN-32){IntDivResultM[31]}}, IntDivResultM[31:0]}, // Sign extending in case of W64
-        W64M, FPIntDivResultM);
+        W64M, FIntDivResultM);
     end else 
-      assign FPIntDivResultM = IntDivResultM[`XLEN-1:0];
+      assign FIntDivResultM = IntDivResultM[`XLEN-1:0];
   end
 endmodule

pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv

@@ -4,28 +4,26 @@
 // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
 // Modified:13 January 2022
 //
-// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
+// Purpose: Divide/Square root preprocessing: integer absolute value and W64, normalization shift
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
@@ -44,10 +42,10 @@ module fdivsqrtpreproc (
   output logic [`DIVb-1:0] DPreproc,
   // Int-specific
   input  logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
-	input  logic MDUE, W64E,
+	input  logic IntDivE, W64E,
   output logic ISpecialCaseE,
   output logic [`DIVBLEN:0] nE, nM, mM,
-  output logic NegQuotM, ALTBM, MDUM, W64M,
+  output logic NegQuotM, ALTBM, IntDivM, W64M,
   output logic AsM, BZeroM,
   output logic [`XLEN-1:0] AM
 );
@@ -95,8 +93,8 @@ module fdivsqrtpreproc (
     mux2 #(`XLEN) posbmux(BE, -BE, BsE, PosB);
 
     // Select integer or floating point inputs
-    mux2 #(`DIVb) ifxmux({Xm, {(`DIVb-`NF-1){1'b0}}}, {PosA, {(`DIVb-`XLEN){1'b0}}}, MDUE, IFNormLenX);
+    mux2 #(`DIVb) ifxmux({Xm, {(`DIVb-`NF-1){1'b0}}}, {PosA, {(`DIVb-`XLEN){1'b0}}}, IntDivE, IFNormLenX);
-    mux2 #(`DIVb) ifdmux({Ym, {(`DIVb-`NF-1){1'b0}}}, {PosB, {(`DIVb-`XLEN){1'b0}}}, MDUE, IFNormLenD);
+    mux2 #(`DIVb) ifdmux({Ym, {(`DIVb-`NF-1){1'b0}}}, {PosB, {(`DIVb-`XLEN){1'b0}}}, IntDivE, IFNormLenD);
 
     // calculate number of fractional bits p
     assign ZeroDiff = mE - ell;         // Difference in number of leading zeros
@@ -126,11 +124,11 @@ module fdivsqrtpreproc (
   /* verilator lint_on WIDTH */
 
     // Selet integer or floating-point operands
-    mux2 #(1)    numzmux(XZeroE, AZeroE, MDUE, NumerZeroE);
+    mux2 #(1)    numzmux(XZeroE, AZeroE, IntDivE, NumerZeroE);
-    mux2 #(`DIVb+4) xmux(PreShiftX, DivXShifted, MDUE, X);
+    mux2 #(`DIVb+4) xmux(PreShiftX, DivXShifted, IntDivE, X);
 
     // pipeline registers
-    flopen #(1)        mdureg(clk, IFDivStartE, MDUE,     MDUM);
+    flopen #(1)        mdureg(clk, IFDivStartE, IntDivE,     IntDivM);
     flopen #(1)        w64reg(clk, IFDivStartE, W64E,     W64M);
     flopen #(1)       altbreg(clk, IFDivStartE, ALTBE,    ALTBM);
     flopen #(1)    negquotreg(clk, IFDivStartE, NegQuotE, NegQuotM);
@@ -155,8 +153,11 @@ module fdivsqrtpreproc (
   assign XPreproc = IFNormLenX << (ell + {{`DIVBLEN{1'b0}}, 1'b1}); 
   assign DPreproc = IFNormLenD << (mE + {{`DIVBLEN{1'b0}}, 1'b1}); 
 
-  // append leading 1 (for nonzero inputs) and conditionally shift left by one to avoid sqrt(2)
+  // append leading 1 (for normal inputs)
-  mux2 #(`DIVb+1) sqrtxmux({~NumerZeroE, XPreproc}, {1'b0, ~NumerZeroE, XPreproc[`DIVb-1:1]}, (Xe[0]^ell[0]), PreSqrtX);
+  // shift square root to be in range [1/4, 1)
+  // Normalized numbers are shifted right by 1 if the exponent is odd
+  // Denormalized numbers have Xe = 0 and an unbiased exponent of 1-BIAS.  They are shifted right if the number of leading zeros is odd.
+  mux2 #(`DIVb+1) sqrtxmux({~XZeroE, XPreproc}, {1'b0, ~XZeroE, XPreproc[`DIVb-1:1]}, (Xe[0] ^ ell[0]), PreSqrtX);
   assign DivX = {3'b000, ~NumerZeroE, XPreproc};
 
   // Sqrt is initialized on step one as R(X-1), so depends on Radix

pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv

@@ -6,26 +6,24 @@
 //
 // Purpose: Radix 2 Quotient Digit Selection
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv

@@ -6,26 +6,24 @@
 //
 // Purpose: Radix 4 Quotient Digit Selection
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv

@@ -6,26 +6,24 @@
 //
 // Purpose: Comparator-based Radix 4 Quotient Digit Selection
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv

@@ -4,28 +4,26 @@
 // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
 // Modified:13 January 2022
 //
-// Purpose: Combined Divide and Square Root Floating Point and Integer Unit stage
+// Purpose: radix-2 divsqrt recurrence stage
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv

@@ -4,28 +4,26 @@
 // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
 // Modified:13 January 2022
 //
-// Purpose: Combined Divide and Square Root Floating Point and Integer Unit stage
+// Purpose: radix-4 divsqrt recurrence stage
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv

@@ -6,26 +6,24 @@
 //
 // Purpose: Radix 2 unified on-the-fly converter
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv

@@ -6,26 +6,24 @@
 //
 // Purpose: Radix 4 unified on-the-fly converter
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/fpu/fhazard.sv

@@ -6,42 +6,40 @@
 //
 // Purpose: Determine forwarding, stalls and flushes for the FPU
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
 
 module fhazard(
-    input  logic [4:0]  Adr1D, Adr2D, Adr3D,    // read data adresses
+    input  logic [4:0]  Adr1D, Adr2D, Adr3D,                // read data adresses
-    input  logic [4:0]  Adr1E, Adr2E, Adr3E,    // read data adresses
+    input  logic [4:0]  Adr1E, Adr2E, Adr3E,                // read data adresses
     input  logic        FRegWriteE, FRegWriteM, FRegWriteW, // is the fp register being written to
-    input  logic [4:0]  RdE, RdM, RdW,               // the adress being written to
+    input  logic [4:0]  RdE, RdM, RdW,                      // the adress being written to
-    input  logic [1:0]  FResSelM,            // the result being selected
+    input  logic [1:0]  FResSelM,                           // the result being selected
-    input  logic        XEnD, YEnD, ZEnD,
+    input  logic        XEnD, YEnD, ZEnD,                   // are the inputs needed
-    output logic        FPUStallD,                // stall the decode stage
+    output logic        FPUStallD,                          // stall the decode stage
-    output logic [1:0]  ForwardXE, ForwardYE, ForwardZE // select a forwarded value
+    output logic [1:0]  ForwardXE, ForwardYE, ForwardZE     // select a forwarded value
 );
 
-  logic                 MatchDE;
+  logic MatchDE; // is a value needed in decode stage being worked on in execute stage
 
   // Decode-stage instruction source depends on result from execute stage instruction
   assign MatchDE = ((Adr1D == RdE) & XEnD) | ((Adr2D == RdE) & YEnD) | ((Adr3D == RdE) & ZEnD);
@@ -58,7 +56,7 @@ module fhazard(
       // if the result will be FResM (can be taken from the memory stage)
       if(FResSelM == 2'b00) ForwardXE = 2'b10; // choose FResM
       // if the needed value is in the writeback stage
-    end else if ((Adr1E == RdW) & FRegWriteW) ForwardXE = 2'b01; // choose FPUResult64W
+    end else if ((Adr1E == RdW) & FRegWriteW) ForwardXE = 2'b01; // choose FResult64W
   
 
     // if the needed value is in the memory stage - input 2
@@ -66,7 +64,7 @@ module fhazard(
       // if the result will be FResM (can be taken from the memory stage)
       if(FResSelM == 2'b00) ForwardYE = 2'b10; // choose FResM
       // if the needed value is in the writeback stage
-    end else if ((Adr2E == RdW) & FRegWriteW) ForwardYE = 2'b01; // choose FPUResult64W
+    end else if ((Adr2E == RdW) & FRegWriteW) ForwardYE = 2'b01; // choose FResult64W
 
 
     // if the needed value is in the memory stage - input 3
@@ -74,7 +72,7 @@ module fhazard(
       // if the result will be FResM (can be taken from the memory stage)
       if(FResSelM == 2'b00) ForwardZE = 2'b10; // choose FResM
       // if the needed value is in the writeback stage
-    end else if ((Adr3E == RdW) & FRegWriteW) ForwardZE = 2'b01; // choose FPUResult64W
+    end else if ((Adr3E == RdW) & FRegWriteW) ForwardZE = 2'b01; // choose FResult64W
 
   end 
 

pipelined/src/fpu/fma/fma.sv

@@ -6,44 +6,42 @@
 //
 // Purpose: Floating point multiply-accumulate of configurable size
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.7, 9)
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
 
 module fma(
-    input logic                         Xs, Ys, Zs, // input's signs
+    input  logic                        Xs, Ys, Zs,             // input's signs
-    input logic  [`NE-1:0]              Xe, Ye, Ze, // input's biased exponents in B(NE.0) format
+    input  logic [`NE-1:0]              Xe, Ye, Ze,             // input's biased exponents in B(NE.0) format
-    input logic  [`NF:0]                Xm, Ym, Zm, // input's significands in U(0.NF) format
+    input  logic [`NF:0]                Xm, Ym, Zm,             // input's significands in U(0.NF) format
-    input logic                         XZero, YZero, ZZero, // is the input zero
+    input  logic                        XZero, YZero, ZZero,    // is the input zero
-    input logic  [2:0]                  OpCtrl,   // operation control
+    input  logic [2:0]                  OpCtrl,                 // operation control
-    output logic                        ASticky,  // sticky bit that is calculated during alignment
+    output logic                        ASticky,                // sticky bit that is calculated during alignment
-    output logic [3*`NF+3:0]            Sm,   // the positive sum's significand
+    output logic [3*`NF+3:0]            Sm,                     // the positive sum's significand
-    output logic                        InvA, // Was A inverted for effective subtraction (P-A or -P+A)
+    output logic                        InvA,                   // Was A inverted for effective subtraction (P-A or -P+A)
-    output logic                        As,   // the aligned addend's sign (modified Z sign for other opperations)
+    output logic                        As,                     // the aligned addend's sign (modified Z sign for other opperations)
-    output logic                        Ps,   // the product's sign
+    output logic                        Ps,                     // the product's sign
-    output logic                        Ss,   // the sum's sign
+    output logic                        Ss,                     // the sum's sign
-    output logic [`NE+1:0]              Se,   // the sum's exponent
+    output logic [`NE+1:0]              Se,                     // the sum's exponent
-    output logic [$clog2(3*`NF+5)-1:0]  SCnt  // normalization shift count
+    output logic [$clog2(3*`NF+5)-1:0]  SCnt                    // normalization shift count
 );
 
     //  OpCtrl:
@@ -56,7 +54,7 @@ module fma(
     //        110 - add
     //        111 - sub
 
-    logic [2*`NF+1:0]   Pm;          // the product's significand in U(2.2Nf) format
+    logic [2*`NF+1:0]   Pm;         // the product's significand in U(2.2Nf) format
     logic [3*`NF+3:0]   Am;         // addend aligned's mantissa for addition in U(NF+4.2NF)
     logic [3*`NF+3:0]   AmInv;      // aligned addend's mantissa possibly inverted
     logic [2*`NF+1:0]   PmKilled;   // the product's mantissa possibly killed U(2.2Nf)
@@ -84,8 +82,7 @@ module fma(
     ///////////////////////////////////////////////////////////////////////////////
     // Alignment shifter
     ///////////////////////////////////////////////////////////////////////////////
-    fmaalign align(.Ze, .Zm, .XZero, .YZero, .ZZero, .Xe, .Ye,
+    fmaalign align(.Ze, .Zm, .XZero, .YZero, .ZZero, .Xe, .Ye, .Am, .ASticky, .KillProd);
-                .Am, .ASticky, .KillProd);
                         
     // ///////////////////////////////////////////////////////////////////////////////
     // // Addition/LZA
@@ -93,7 +90,7 @@ module fma(
         
     fmaadd add(.Am, .Pm, .Ze, .Pe, .Ps, .KillProd, .ASticky, .AmInv, .PmKilled, .InvA, .Sm, .Se, .Ss);
 
-    fmalza #(3*`NF+4) lza(.A(AmInv), .Pm({PmKilled, InvA&Ps&ASticky&KillProd}), .Cin(InvA & ~(ASticky & ~KillProd)), .sub(InvA), .SCnt);
+    fmalza #(3*`NF+4) lza(.A(AmInv), .Pm(PmKilled), .Cin(InvA & (~ASticky | KillProd)), .sub(InvA), .SCnt);
     
 endmodule
 

pipelined/src/fpu/fma/fmaadd.sv

@@ -6,48 +6,45 @@
 //
 // Purpose: FMA significand adder
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.11)
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
 
 module fmaadd(
-    input logic  [3*`NF+3:0]    Am, // aligned addend's mantissa for addition in U(NF+5.2NF+1)
+    input  logic [3*`NF+3:0]    Am,         // aligned addend's mantissa for addition in U(NF+5.2NF+1)
-    input logic  [2*`NF+1:0]    Pm,       // the product's mantissa
+    input  logic [`NE-1:0]      Ze,         // exponent of Z
-    input logic                 Ps, // the product sign and the alligend addeded's sign (Modified Z sign for other opperations)
+    input  logic                Ps,         // the product sign and the alligend addeded's sign (Modified Z sign for other opperations)
-    input logic                 InvA,          // invert the aligned addend
+    input  logic [`NE+1:0]      Pe,         // product's exponet
-    input logic                 KillProd,      // should the product be set to 0
+    input  logic [2*`NF+1:0]    Pm,         // the product's mantissa
-    input logic                 ASticky,
+    input  logic                InvA,       // invert the aligned addend
-    input logic  [`NE-1:0]      Ze,
+    input  logic                KillProd,   // should the product be set to 0
-    input logic  [`NE+1:0]      Pe,
+    input  logic                ASticky,    // Alighed addend's sticky bit
-    output logic [3*`NF+3:0]    AmInv, // aligned addend possibly inverted
+    output logic [3*`NF+3:0]    AmInv,      // aligned addend possibly inverted
-    output logic [2*`NF+1:0]    PmKilled,     // the product's mantissa possibly killed
+    output logic [2*`NF+1:0]    PmKilled,   // the product's mantissa possibly killed
-    output logic                Ss,          
+    output logic                Ss,         // sum's sign    
-    output logic [`NE+1:0]      Se,
+    output logic [`NE+1:0]      Se,         // sum's exponent
     output logic [3*`NF+3:0]    Sm          // the positive sum
 );
     logic [3*`NF+3:0]    PreSum, NegPreSum; // possibly negitive sum
-    logic                NegSum;        // was the sum negitive
+    logic                NegSum;            // was the sum negitive
-    logic                NegSumdebug;        // was the sum negitive
 
     ///////////////////////////////////////////////////////////////////////////////
     // Addition

pipelined/src/fpu/fma/fmaalign.sv

@@ -7,43 +7,41 @@
 //
 // Purpose: FMA alginment shift
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.10)
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
 
 module fmaalign(
-    input logic  [`NE-1:0]      Xe, Ye, Ze,      // biased exponents in B(NE.0) format
+    input  logic [`NE-1:0]      Xe, Ye, Ze,         // biased exponents in B(NE.0) format
-    input logic  [`NF:0]        Zm,      // significand in U(0.NF) format]
+    input  logic [`NF:0]        Zm,                 // significand in U(0.NF) format]
-    input logic                 XZero, YZero, ZZero, // is the input zero
+    input  logic                XZero, YZero, ZZero,// is the input zero
-    output logic [3*`NF+3:0]    Am, // addend aligned for addition in U(NF+5.2NF+1)
+    output logic [3*`NF+3:0]    Am,                 // addend aligned for addition in U(NF+5.2NF+1)
-    output logic                ASticky,  // Sticky bit calculated from the aliged addend
+    output logic                ASticky,            // Sticky bit calculated from the aliged addend
-    output logic                KillProd       // should the product be set to zero
+    output logic                KillProd            // should the product be set to zero
 );
 
     logic [`NE+1:0]     ACnt;           // how far to shift the addend to align with the product in Q(NE+2.0) format
-    logic [4*`NF+3:0]   ZmShifted;        // output of the alignment shifter including sticky bits U(NF+5.3NF+1)
+    logic [4*`NF+3:0]   ZmShifted;      // output of the alignment shifter including sticky bits U(NF+5.3NF+1)
-    logic [4*`NF+3:0]   ZmPreshifted;     // input to the alignment shifter U(NF+5.3NF+1)
+    logic [4*`NF+3:0]   ZmPreshifted;   // input to the alignment shifter U(NF+5.3NF+1)
-    logic KillZ;
+    logic               KillZ;          // should the addend be killed
 
     ///////////////////////////////////////////////////////////////////////////////
     // Alignment shifter

pipelined/src/fpu/fma/fmaexpadd.sv

@@ -6,37 +6,35 @@
 //
 // Purpose: FMA exponent addition
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.9)
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
 
 module fmaexpadd(    
-    input  logic [`NE-1:0]      Xe, Ye,  // input's exponents
+    input  logic [`NE-1:0]      Xe, Ye,         // input's exponents
-    input  logic                XZero, YZero,        // are the inputs zero
+    input  logic                XZero, YZero,   // are the inputs zero
-    output logic [`NE+1:0]      Pe       // product's exponent B^(1023)NE+2
+    output logic [`NE+1:0]      Pe              // product's exponent B^(1023)NE+2
 );
 
-   logic 			PZero;
+   logic PZero; // is the product zero
    
     // kill the exponent if the product is zero - either X or Y is 0
    assign PZero = XZero | YZero;

pipelined/src/fpu/fma/fmalza.sv

@@ -6,43 +6,41 @@
 //
 // Purpose: Leading Zero Anticipator
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.14)
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
 
 module fmalza #(WIDTH) ( // [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001]
     input logic [WIDTH-1:0]             A,      // addend
-    input logic [2*`NF+2:0]             Pm,     // product
+    input logic [2*`NF+1:0]             Pm,     // product
     input logic 		                Cin,    // carry in
-    input logic                         sub,
+    input logic                         sub,    // subtraction
     output logic [$clog2(WIDTH+1)-1:0]  SCnt    // normalization shift count for the positive result
     ); 
 
-   logic [WIDTH:0] 	       F;
+   logic [WIDTH:0] 	  F;
    logic [WIDTH-1:0]  B, P, Guard, K;
     logic [WIDTH-1:0] Pp1, Gm1, Km1;
 
-    assign B = {{(`NF+1){1'b0}}, Pm}; // Zero extend product
+    assign B = {{(`NF+1){1'b0}}, Pm, 1'b0}; // Zero extend product
 
     assign P = A^B;
     assign Guard = A&B;

pipelined/src/fpu/fma/fmamult.sv

@@ -6,33 +6,31 @@
 //
 // Purpose: FMA Significand Multiplier
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.7)
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
 
 module fmamult(
-    input logic [`NF:0] Xm, Ym,
+    input  logic [`NF:0]     Xm, Ym, // x and y significand
-    output logic [2*`NF+1:0] Pm
+    output logic [2*`NF+1:0] Pm      // product's significand
 );
     assign Pm = Xm * Ym;
 endmodule

pipelined/src/fpu/fma/fmasign.sv

@@ -6,41 +6,38 @@
 //
 // Purpose: FMA Sign Logic
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.8)
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
 
 module fmasign(    
-    input  logic [2:0]  OpCtrl,               // opperation contol
+    input  logic [2:0]  OpCtrl,     // opperation contol
-    input  logic        Xs, Ys, Zs,    // sign of the inputs
+    input  logic        Xs, Ys, Zs, // sign of the inputs
-    output logic        Ps,     // the product's sign - takes opperation into account
+    output logic        Ps,         // the product's sign - takes opperation into account
-    output logic        As,   // aligned addend sign used in fma - takes opperation into account
+    output logic        As,         // aligned addend sign used in fma - takes opperation into account
-    output logic        InvA // Effective subtraction: invert addend
+    output logic        InvA        // Effective subtraction: invert addend
 );
 
     // Calculate the product's sign
     //      Negate product's sign if FNMADD or FNMSUB
-    
     // flip is negation opperation
     assign Ps = Xs ^ Ys ^ (OpCtrl[1]&~OpCtrl[2]);
     // flip addend sign for subtraction

pipelined/src/fpu/fpu.sv

@@ -1,31 +1,29 @@
 ///////////////////////////////////////////
 // fpu.sv
 //
-// Written: me@KatherineParry.com, James Stine, Brett Mathis
+// Written: me@KatherineParry.com, James Stine, Brett Mathis, David Harris
 // Modified: 6/23/2021
 //
-// Purpose: FPU
+// Purpose: Floating Point Unit Top-Level Interface
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
@@ -33,148 +31,153 @@
 module fpu (
    input  logic 		        clk,
    input  logic 		        reset,
-   input  logic  [2:0] 	     FRM_REGW,   // Rounding mode (from CSR)
+   // Hazards
-   input  logic  [31:0] 	  InstrD,     // instruction (from IFU)
-   input  logic  [`FLEN-1:0] ReadDataW,  // Read data (from LSU)
-   input  logic  [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // Integer input (from IEU)
    input  logic 		        StallE, StallM, StallW, // stall signals (from HZU)
    input  logic 		        FlushE, FlushM, FlushW, // flush signals (from HZU)
-   input  logic  [4:0] 	     RdE, RdM, RdW,   // which FP register to write to (from IEU)
+   output logic 		        FPUStallD,     // Stall the decode stage (To HZU)
-   input  logic  [1:0]       STATUS_FS,  // Is floating-point enabled? (From privileged unit)
+   output logic 		        FDivBusyE,     // Is the divide/sqrt unit busy (stall execute stage) (to HZU)
-   input  logic  [2:0] 	     Funct3E, Funct3M,
+   // CSRs
-	input  logic 		        MDUE, W64E,
+   input  logic [1:0]        STATUS_FS,     // Is floating-point enabled? (From privileged unit)
-   output logic 		        FRegWriteM, // FP register write enable (to privileged unit)
+   input  logic [2:0] 	     FRM_REGW,      // Rounding mode (from CSR)
-   output logic 		        FpLoadStoreM,  // Fp load instruction? (to LSU)
+   // Decode stage 
-   output logic 		        FPUStallD,       // Stall the decode stage (To HZU)
+   input  logic [31:0] 	     InstrD,        // instruction (from IFU)
+   // Execute stage 
+   input  logic [2:0] 	     Funct3E,       // Funct fields of instruction specify type of operations
+	input  logic 		        IntDivE, W64E, // Integer division on FPU
+   input  logic [`XLEN-1:0]  ForwardedSrcAE, ForwardedSrcBE, // Integer input for convert, move, and int div (from IEU)
+   input  logic [4:0] 	     RdE,           // which FP register to write to (from IEU)
    output logic 		        FWriteIntE,    // integer register write enable (to IEU)
    output logic              FCvtIntE,      // Convert to int (to IEU)
+   // Memory stage 
+   input  logic [2:0] 	     Funct3M,       // Funct fields of instruction specify type of operations
+   input  logic [4:0] 	     RdM,           // which FP register to write to (from IEU)
+   output logic 		        FRegWriteM,    // FP register write enable (to privileged unit)
+   output logic 		        FpLoadStoreM,  // Fp load instruction? (to LSU)
    output logic [`FLEN-1:0]  FWriteDataM,   // Data to be written to memory (to LSU) 
    output logic [`XLEN-1:0]  FIntResM,      // data to be written to integer register (to IEU)
+   output logic 		        IllegalFPUInstrM, // Is the instruction an illegal fpu instruction (to privileged unit)
+   output logic [4:0] 	     SetFflagsM,    // FPU flags (to privileged unit)
+   // Writeback stage 
+   input  logic [4:0] 	     RdW,           // which FP register to write to (from IEU)
+   input  logic [`FLEN-1:0]  ReadDataW,     // Read data (from LSU)
    output logic [`XLEN-1:0]  FCvtIntResW,   // convert result to to be written to integer register (to IEU)
    output logic              FCvtIntW,      // select FCvtIntRes (to IEU)
-   output logic 		        FDivBusyE,     // Is the divide/sqrt unit busy (stall execute stage) (to HZU)
+   output logic [`XLEN-1:0]  FIntDivResultW // Result from integer division (to IEU)
-   output logic 		        IllegalFPUInstrM, // Is the instruction an illegal fpu instruction (to privileged unit)
+);
-   output logic [4:0] 	     SetFflagsM,        // FPU flags (to privileged unit)
-   output logic [`XLEN-1:0]  FPIntDivResultW
-  );
 
-   // FPU specifics:
+   // RISC-V FPU specifics:
-   //    - uses NaN-blocking format
+   //    - multiprecision support uses NAN-boxing, putting 1's in unused msbs
-   //        - if there are any unsused bits the most significant bits are filled with 1s
+   //    - RISC-V detects underflow after rounding
-   //                single stored in a double: | 32 1s | single precision value |
-   //    - sets the underflow after rounding
 
    // control signals
-   logic 		         FRegWriteW; // FP register write enable
+   logic 		         FRegWriteW;                        // FP register write enable
-   logic [2:0] 	      FrmM;                   // FP rounding mode
+   logic [2:0] 	      FrmM;                              // FP rounding mode
-   logic [`FMTBITS-1:0] FmtE, FmtM;             // FP precision 0-single 1-double
+   logic [`FMTBITS-1:0] FmtE, FmtM;                        // FP precision 0-single 1-double
-   logic 		         FDivStartE, IDivStartE;             // Start division or squareroot
+   logic 		         FDivStartE, IDivStartE;            // Start division or squareroot
-   logic 		         FWriteIntM;                         // Write to integer register
+   logic 		         FWriteIntM;                        // Write to integer register
-   logic [1:0] 	      ForwardXE, ForwardYE, ForwardZE; // forwarding mux control signals
+   logic [1:0] 	      ForwardXE, ForwardYE, ForwardZE;   // forwarding mux control signals
-   logic [2:0] 	      OpCtrlE, OpCtrlM;       // Select which opperation to do in each component
+   logic [2:0] 	      OpCtrlE, OpCtrlM;                  // Select which opperation to do in each component
-   logic [1:0] 	      FResSelE, FResSelM, FResSelW;       // Select one of the results that finish in the memory stage
+   logic [1:0] 	      FResSelE, FResSelM, FResSelW;      // Select one of the results that finish in the memory stage
-   logic [1:0] 	      PostProcSelE, PostProcSelM; // select result in the post processing unit
+   logic [1:0] 	      PostProcSelE, PostProcSelM;        // select result in the post processing unit
-   logic [4:0] 	      Adr1D, Adr2D, Adr3D;                // adresses of each input
+   logic [4:0] 	      Adr1D, Adr2D, Adr3D;               // register adresses of each input
-   logic [4:0] 	      Adr1E, Adr2E, Adr3E;                // adresses of each input
+   logic [4:0] 	      Adr1E, Adr2E, Adr3E;               // register adresses of each input
-   logic                XEnD, YEnD, ZEnD;
+   logic                XEnD, YEnD, ZEnD;                  // X, Y, Z inputs used for current operation
-   logic                XEnE, YEnE, ZEnE;
+   logic                XEnE, YEnE, ZEnE;                  // X, Y, Z inputs used for current operation
-   logic                 FRegWriteE;
+   logic                FRegWriteE;                        // Write floating-point register
 
    // regfile signals
-   logic [`FLEN-1:0] FRD1D, FRD2D, FRD3D;                // Read Data from FP register - decode stage
+   logic [`FLEN-1:0] FRD1D, FRD2D, FRD3D;                  // Read Data from FP register - decode stage
-   logic [`FLEN-1:0] FRD1E, FRD2E, FRD3E;                // Read Data from FP register - execute stage
+   logic [`FLEN-1:0] FRD1E, FRD2E, FRD3E;                  // Read Data from FP register - execute stage
-   logic [`FLEN-1:0] XE;                             // Input 1 to the various units (after forwarding)
+   logic [`FLEN-1:0] XE;                                   // Input 1 to the various units (after forwarding)
    logic [`XLEN-1:0] IntSrcXE;                             // Input 1 to the various units (after forwarding)
-   logic [`FLEN-1:0] PreYE, YE;                  // Input 2 to the various units (after forwarding)
+   logic [`FLEN-1:0] PreYE, YE;                            // Input 2 to the various units (after forwarding)
-   logic [`FLEN-1:0] PreZE, ZE;                  // Input 3 to the various units (after forwarding)
+   logic [`FLEN-1:0] PreZE, ZE;                            // Input 3 to the various units (after forwarding)
 
    // unpacking signals
-   logic 		      XsE, YsE, ZsE;                // input's sign - execute stage
+   logic 		      XsE, YsE, ZsE;                        // input's sign - execute stage
-   logic 		      XsM, YsM;                       // input's sign - memory stage
+   logic 		      XsM, YsM;                             // input's sign - memory stage
-   logic [`NE-1:0] 	XeE, YeE, ZeE;                // input's exponent - execute stage
+   logic [`NE-1:0] 	XeE, YeE, ZeE;                        // input's exponent - execute stage
-   logic [`NE-1:0] 	ZeM;                              // input's exponent - memory stage
+   logic [`NE-1:0] 	ZeM;                                  // input's exponent - memory stage
-   logic [`NF:0] 	   XmE, YmE, ZmE;                // input's fraction - execute stage
+   logic [`NF:0] 	   XmE, YmE, ZmE;                        // input's significand - execute stage
-   logic [`NF:0] 	   XmM, YmM, ZmM;                // input's fraction - memory stage
+   logic [`NF:0] 	   XmM, YmM, ZmM;                        // input's significand - memory stage
-   logic 		      XNaNE, YNaNE, ZNaNE;                // is the input a NaN - execute stage
+   logic 		      XNaNE, YNaNE, ZNaNE;                  // is the input a NaN - execute stage
-   logic 		      XNaNM, YNaNM, ZNaNM;                // is the input a NaN - memory stage
+   logic 		      XNaNM, YNaNM, ZNaNM;                  // is the input a NaN - memory stage
-   logic 		      XSNaNE, YSNaNE, ZSNaNE;             // is the input a signaling NaN - execute stage
+   logic 		      XSNaNE, YSNaNE, ZSNaNE;               // is the input a signaling NaN - execute stage
-   logic 		      XSNaNM, YSNaNM, ZSNaNM;             // is the input a signaling NaN - memory stage
+   logic 		      XSNaNM, YSNaNM, ZSNaNM;               // is the input a signaling NaN - memory stage
-   logic 		      XSubnormE;       // is the input Subnormalized
+   logic 		      XSubnormE;                            // is the input subnormal
-   logic 		      XZeroE, YZeroE, ZZeroE;             // is the input zero - execute stage
+   logic 		      XZeroE, YZeroE, ZZeroE;               // is the input zero - execute stage
-   logic 		      XZeroM, YZeroM;             // is the input zero - memory stage
+   logic 		      XZeroM, YZeroM;                       // is the input zero - memory stage
-   logic 		      XInfE, YInfE, ZInfE;                // is the input infinity - execute stage
+   logic 		      XInfE, YInfE, ZInfE;                  // is the input infinity - execute stage
-   logic 		      XInfM, YInfM, ZInfM;                // is the input infinity - memory stage
+   logic 		      XInfM, YInfM, ZInfM;                  // is the input infinity - memory stage
-   logic 		      XExpMaxE;                           // is the exponent all ones (max value)
+   logic 		      XExpMaxE;                             // is the exponent all ones (max value)
 
    // Fma Signals
-   logic [3*`NF+3:0] SmE, SmM;            
+   logic             FmaAddSubE;                           // Multiply by 1.0 when adding or subtracting
-   logic 			   FmaAStickyE, FmaAStickyM;
+   logic [1:0]       FmaZSelE;                             // Select Z = Y when adding or subtracting, 0 when multiplying
-   logic [`NE+1:0]   SeE,SeM;
+   logic [3*`NF+3:0] SmE, SmM;                             // Sum significand
-   logic 			   InvAE, InvAM;
+   logic 			   FmaAStickyE, FmaAStickyM;             // FMA addend sticky bit output
-   logic 			   AsE, AsM;
+   logic [`NE+1:0]   SeE,SeM;                              // Sum exponent
-   logic 			   PsE, PsM;
+   logic 			   InvAE, InvAM;                         // Invert addend
-   logic 			   SsE, SsM;
+   logic 			   AsE, AsM;                             // Addend sign
-   logic [$clog2(3*`NF+5)-1:0] SCntE, SCntM;
+   logic 			   PsE, PsM;                             // Product sign
+   logic 			   SsE, SsM;                             // Sum sign
+   logic [$clog2(3*`NF+5)-1:0] SCntE, SCntM;               // LZA sum leading zero count
    
    // Cvt Signals
-   logic [`NE:0]           CeE, CeM;    // the calculated expoent
+   logic [`NE:0]           CeE, CeM;                       // convert intermediate expoent
-   logic [`LOGCVTLEN-1:0]  CvtShiftAmtE, CvtShiftAmtM;  // how much to shift by
+   logic [`LOGCVTLEN-1:0]  CvtShiftAmtE, CvtShiftAmtM;     // how much to shift by
-   logic                   CvtResSubnormUfE, CvtResSubnormUfM;// does the result underflow or is Subnormalized
+   logic                   CvtResSubnormUfE, CvtResSubnormUfM; // does the result underflow or is subnormal
-   logic                   CsE, CsM;     // the result's sign
+   logic                   CsE, CsM;                       // convert result sign
-   logic                   IntZeroE, IntZeroM;      // is the integer zero?
+   logic                   IntZeroE, IntZeroM;             // is the integer zero?
-   logic [`CVTLEN-1:0]     CvtLzcInE, CvtLzcInM;      // input to the Leading Zero Counter (priority encoder)
+   logic [`CVTLEN-1:0]     CvtLzcInE, CvtLzcInM;           // input to the Leading Zero Counter (priority encoder)
+   logic [`XLEN-1:0]       FCvtIntResM;                    // fcvt integer result (for IEU)
    
-   //divide signals
+   // divide signals
-   logic [`DIVb:0]      QmM;
+   logic [`DIVb:0]      QmM;                               // fdivsqrt signifcand
-   logic [`NE+1:0]      QeM; 
+   logic [`NE+1:0]      QeM;                               // fdivsqrt exponent
-   logic                DivSM;
+   logic                DivStickyM;                        // fdivsqrt sticky bit
-   logic                FDivDoneE, IFDivStartE;
+   logic                FDivDoneE, IFDivStartE;            // fdivsqrt control signals
+   logic [`XLEN-1:0]    FIntDivResultM;                    // fdivsqrt integer division result (for IEU)
 
    // result and flag signals
-   logic [`XLEN-1:0] ClassResE;               // classify result
+   logic [`XLEN-1:0] ClassResE;                            // classify result
-   logic [`XLEN-1:0] FIntResE;               // classify result
+   logic [`FLEN-1:0] CmpFpResE;                            // compare result to FPU (min/max)
-   logic [`FLEN-1:0] FpResM, FpResW;               // classify result
+   logic [`XLEN-1:0] CmpIntResE;                           // compare result to IEU (eq/lt/le)
-   logic [`FLEN-1:0] PostProcResM;               // classify result
+   logic 		      CmpNVE;                               // compare invalid flag (Not Valid)     
-   logic [4:0] 	   PostProcFlgM;               // classify result
+   logic [`FLEN-1:0] SgnResE;                              // sign injection result
-   logic [`XLEN-1:0] FCvtIntResM; 
+   logic [`XLEN-1:0] FIntResE;                             // FPU to IEU E-stage result (classify, compare, move)
-   logic [`FLEN-1:0] CmpFpResE;                   // compare result
+   logic [`FLEN-1:0] PostProcResM;                         // Postprocessor output
-   logic [`XLEN-1:0] CmpIntResE;                   // compare result
+   logic [4:0] 	   PostProcFlgM;                         // Postprocessor flags
-   logic 		      CmpNVE;                     // compare invalid flag (Not Valid)     
-   logic [`FLEN-1:0] SgnResE;                   // sign injection result
-   logic [`FLEN-1:0] PreFpResE, PreFpResM;                // selected result that is ready in the memory stage
    logic  	         PreNVE, PreNVM;                       // selected flag that is ready in the memory stage     
-   logic [`FLEN-1:0] FPUResultW;                         // final FP result being written to the FP register     
+   logic [`FLEN-1:0] FpResM, FpResW;                       // FPU preliminary result
-   // other signals
+   logic [`FLEN-1:0] PreFpResE, PreFpResM;                 // selected result that is ready in the memory stage
-   logic [`FLEN-1:0] 	 AlignedSrcAE;                       // align SrcA to the floating point format
+   logic [`FLEN-1:0] FResultW;                             // final FP result being written to the FP register   
-   logic [`FLEN-1:0]     BoxedZeroE;                         // Zero value for Z for multiplication, with NaN boxing if needed
-   logic [`FLEN-1:0]     BoxedOneE;                         // Zero value for Z for multiplication, with NaN boxing if needed
-   logic             StallUnpackedM;
-   logic [`XLEN-1:0] FPIntDivResultM;
 
-   // DECODE STAGE
+   // other signals
+   logic [`FLEN-1:0] AlignedSrcAE;                         // align SrcA from IEU to the floating point format for fmv
+   logic [`FLEN-1:0] BoxedZeroE;                           // Zero value for Z for multiplication, with NaN boxing if needed
+   logic [`FLEN-1:0] BoxedOneE;                            // One value for Z for multiplication, with NaN boxing if needed
+   logic             StallUnpackedM;                       // Stall unpacker outputs during multicycle fdivsqrt
+   logic [`FLEN-1:0] SgnExtXE;                             // Sign-extended X input for move to integer
 
    //////////////////////////////////////////////////////////////////////////////////////////
-   //          |||||||||||
+   // Decode Stage: fctrl decoder, read register file
-   //          |||      |||
-   //          |||       |||
-   //          |||       |||
-   //          |||       |||
-   //          |||      |||
-   //          |||||||||||
    //////////////////////////////////////////////////////////////////////////////////////////
 
    // calculate FP control signals
    fctrl fctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]), 
-               .Funct3E, .MDUE, .InstrD,
+               .Funct3E, .IntDivE, .InstrD,
                .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, .FRM_REGW, .STATUS_FS, .FDivBusyE,
                .reset, .clk, .FRegWriteE, .FRegWriteM, .FRegWriteW, .FrmM, .FmtE, .FmtM,
-               .FDivStartE, .IDivStartE, .FWriteIntE, .FCvtIntE, .FWriteIntM, .OpCtrlE, .OpCtrlM, .IllegalFPUInstrM, .XEnD, .YEnD, .ZEnD, .XEnE, .YEnE, .ZEnE,
+               .FDivStartE, .IDivStartE, .FWriteIntE, .FCvtIntE, .FWriteIntM, .OpCtrlE, .OpCtrlM, .FpLoadStoreM,
-               .FResSelE, .FResSelM, .FResSelW, .PostProcSelE, .PostProcSelM, .FCvtIntW, .Adr1D, .Adr2D, .Adr3D, .Adr1E, .Adr2E, .Adr3E);
+               .IllegalFPUInstrM, .XEnD, .YEnD, .ZEnD, .XEnE, .YEnE, .ZEnE,
+               .FResSelE, .FResSelM, .FResSelW, .PostProcSelE, .PostProcSelM, .FCvtIntW, 
+               .Adr1D, .Adr2D, .Adr3D, .Adr1E, .Adr2E, .Adr3E);
 
    // FP register file
    fregfile fregfile (.clk, .reset, .we4(FRegWriteW),
       .a1(InstrD[19:15]), .a2(InstrD[24:20]), .a3(InstrD[31:27]), 
-      .a4(RdW), .wd4(FPUResultW),
+      .a4(RdW), .wd4(FResultW),
       .rd1(FRD1D), .rd2(FRD2D), .rd3(FRD3D));	
 
    // D/E pipeline registers  
@@ -182,29 +185,21 @@ module fpu (
    flopenrc #(`FLEN) DEReg2(clk, reset, FlushE, ~StallE, FRD2D, FRD2E);
    flopenrc #(`FLEN) DEReg3(clk, reset, FlushE, ~StallE, FRD3D, FRD3E);
 
-   // EXECUTION STAGE
-   
    //////////////////////////////////////////////////////////////////////////////////////////
-   //          ||||||||||||
+   // Execute Stage: hazards, forwarding, unpacking, execution units
-   //          |||
-   //          |||       
-   //          |||||||||
-   //          |||     
-   //          |||      
-   //          ||||||||||||
    //////////////////////////////////////////////////////////////////////////////////////////
 
-   // Hazard unit for FPU  
+   // Hazard unit for FPU: determines if any forwarding or stalls are needed
-   //    - determines if any forwarding or stalls are needed
+   fhazard fhazard(.Adr1D, .Adr2D, .Adr3D, .Adr1E, .Adr2E, .Adr3E, 
-   fhazard fhazard(.Adr1D, .Adr2D, .Adr3D, .Adr1E, .Adr2E, .Adr3E, .FRegWriteE, .FRegWriteM, .FRegWriteW, .RdE, .RdM, .RdW, .FResSelM, 
+      .FRegWriteE, .FRegWriteM, .FRegWriteW, .RdE, .RdM, .RdW, .FResSelM, 
-                   .XEnD, .YEnD, .ZEnD, .FPUStallD, .ForwardXE, .ForwardYE, .ForwardZE);
+      .XEnD, .YEnD, .ZEnD, .FPUStallD, .ForwardXE, .ForwardYE, .ForwardZE);
 
    // forwarding muxs
-   mux3  #(`FLEN)  fxemux (FRD1E, FPUResultW, PreFpResM, ForwardXE, XE);
+   mux3  #(`FLEN)  fxemux (FRD1E, FResultW, PreFpResM, ForwardXE, XE);
-   mux3  #(`FLEN)  fyemux (FRD2E, FPUResultW, PreFpResM, ForwardYE, PreYE);
+   mux3  #(`FLEN)  fyemux (FRD2E, FResultW, PreFpResM, ForwardYE, PreYE);
-   mux3  #(`FLEN)  fzemux (FRD3E, FPUResultW, PreFpResM, ForwardZE, PreZE);
+   mux3  #(`FLEN)  fzemux (FRD3E, FResultW, PreFpResM, ForwardZE, PreZE);
-
 
+   // Select NAN-boxed value of Y = 1.0 in proper format for fma to add/subtract X*Y+Z
    generate
       if(`FPSIZES == 1) assign BoxedOneE = {2'b0, {`NE-1{1'b1}}, (`NF)'(0)};
       else if(`FPSIZES == 2) 
@@ -215,11 +210,11 @@ module fpu (
                               {{`FLEN-`H_LEN{1'b1}}, 2'b0, {`H_NE-1{1'b1}}, (`H_NF)'(0)}, 
                               {2'b0, {`NE-1{1'b1}}, (`NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes
    endgenerate
+   assign FmaAddSubE = OpCtrlE[2]&OpCtrlE[1]&(FResSelE==2'b01)&(PostProcSelE==2'b10);
+   mux2  #(`FLEN)  fyaddmux (PreYE, BoxedOneE, FmaAddSubE, YE); // Force Y to be 1 for add/subtract
    
-
+   // Select NAN-boxed value of Z = 0.0 in proper format for FMA for multiply X*Y+Z
-   mux2  #(`FLEN)  fyaddmux (PreYE, BoxedOneE, OpCtrlE[2]&OpCtrlE[1]&(FResSelE==2'b01)&(PostProcSelE==2'b10), YE); // Force Z to be 0 for multiply instructions
+   // For add and subtract, Z comes from second source operand
-   
-   // Force Z to be 0 for multiply instructions 
    generate
    if(`FPSIZES == 1) assign BoxedZeroE = 0;
    else if(`FPSIZES == 2) 
@@ -230,74 +225,49 @@ module fpu (
                                  {{`FLEN-`H_LEN{1'b1}}, {`H_LEN{1'b0}}}, 
                                  (`FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes
    endgenerate
+   assign FmaZSelE = {OpCtrlE[2]&OpCtrlE[1], OpCtrlE[2]&~OpCtrlE[1]};
+   mux3  #(`FLEN)  fzmulmux (PreZE, BoxedZeroE, PreYE, FmaZSelE, ZE);
 
-   mux3  #(`FLEN)  fzmulmux (PreZE, BoxedZeroE, PreYE, {OpCtrlE[2]&OpCtrlE[1], OpCtrlE[2]&~OpCtrlE[1]}, ZE);
+   // unpack unit: splits FP inputs into their parts and classifies SNaN, NaN, Subnorm, Norm, Zero, Infifnity
-
-   // unpack unit
-   //    - splits FP inputs into their various parts
-   //    - does some classifications (SNaN, NaN, Subnorm, Norm, Zero, Infifnity)
    unpack unpack (.X(XE), .Y(YE), .Z(ZE), .Fmt(FmtE), .Xs(XsE), .Ys(YsE), .Zs(ZsE), 
-                  .Xe(XeE), .Ye(YeE), .Ze(ZeE), .Xm(XmE), .Ym(YmE), .Zm(ZmE), .YEn(YEnE),
+      .Xe(XeE), .Ye(YeE), .Ze(ZeE), .Xm(XmE), .Ym(YmE), .Zm(ZmE), .YEn(YEnE),
-                  .XNaN(XNaNE), .YNaN(YNaNE), .ZNaN(ZNaNE), .XSNaN(XSNaNE), .XEn(XEnE), 
+      .XNaN(XNaNE), .YNaN(YNaNE), .ZNaN(ZNaNE), .XSNaN(XSNaNE), .XEn(XEnE), 
-                  .YSNaN(YSNaNE), .ZSNaN(ZSNaNE), .XSubnorm(XSubnormE), 
+      .YSNaN(YSNaNE), .ZSNaN(ZSNaNE), .XSubnorm(XSubnormE), 
-                  .XZero(XZeroE), .YZero(YZeroE), .ZZero(ZZeroE), .XInf(XInfE), .YInf(YInfE), 
+      .XZero(XZeroE), .YZero(YZeroE), .ZZero(ZZeroE), .XInf(XInfE), .YInf(YInfE), 
-                  .ZEn(ZEnE), .ZInf(ZInfE), .XExpMax(XExpMaxE));
+      .ZEn(ZEnE), .ZInf(ZInfE), .XExpMax(XExpMaxE));
    
-   // fused multiply add
+   // fused multiply add: fadd/sub, fmul, fmadd/fnmadd/fmsub/fnmsub
-   //    - fadd/fsub
+   fma fma (.Xs(XsE), .Ys(YsE), .Zs(ZsE), .Xe(XeE), .Ye(YeE), .Ze(ZeE), .Xm(XmE), .Ym(YmE), .Zm(ZmE), 
-   //    - fmul
+      .XZero(XZeroE), .YZero(YZeroE), .ZZero(ZZeroE), .OpCtrl(OpCtrlE), 
-   //    - fmadd/fnmadd/fmsub/fnmsub
+      .As(AsE), .Ps(PsE), .Ss(SsE), .Se(SeE), .Sm(SmE), .InvA(InvAE), .SCnt(SCntE), .ASticky(FmaAStickyE)); 
-   fma fma (.Xs(XsE), .Ys(YsE), .Zs(ZsE), 
-            .Xe(XeE), .Ye(YeE), .Ze(ZeE), 
-            .Xm(XmE), .Ym(YmE), .Zm(ZmE), 
-            .XZero(XZeroE), .YZero(YZeroE), .ZZero(ZZeroE), 
-            .OpCtrl(OpCtrlE), 
-            .As(AsE), .Ps(PsE), .Ss(SsE), .Se(SeE),
-            .Sm(SmE), 
-            .InvA(InvAE), .SCnt(SCntE), 
-            .ASticky(FmaAStickyE)); 
 
-   // divide and squareroot
+   // divide and square root: fdiv, fsqrt, optionally integer division
-   //    - fdiv
-   //    - fsqrt
-   // *** add other opperations
    fdivsqrt fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]),
-                  .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .FDivStartE, .IDivStartE, .XsE,
+      .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .FDivStartE, .IDivStartE, .XsE,
-                  .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E,
+      .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .IntDivE, .W64E,
-                  .StallM, .FlushE, .DivSM, .FDivBusyE, .IFDivStartE, .FDivDoneE, .QeM, 
+      .StallM, .FlushE, .DivStickyM, .FDivBusyE, .IFDivStartE, .FDivDoneE, .QeM, 
-                  .QmM, .FPIntDivResultM /*, .DivDone(DivDoneM) */);
+      .QmM, .FIntDivResultM);
 
-                  //
+   // compare: fmin/fmax, flt/fle/feq
-   // compare
-   //    - fmin/fmax
-   //    - flt/fle/feq
    fcmp fcmp (.Fmt(FmtE), .OpCtrl(OpCtrlE), .Xs(XsE), .Ys(YsE), .Xe(XeE), .Ye(YeE), 
-               .Xm(XmE), .Ym(YmE), .XZero(XZeroE), .YZero(YZeroE), .XNaN(XNaNE), .YNaN(YNaNE), 
+      .Xm(XmE), .Ym(YmE), .XZero(XZeroE), .YZero(YZeroE), .XNaN(XNaNE), .YNaN(YNaNE), 
-               .XSNaN(XSNaNE), .YSNaN(YSNaNE), .X(XE), .Y(YE), .CmpNV(CmpNVE), 
+      .XSNaN(XSNaNE), .YSNaN(YSNaNE), .X(XE), .Y(YE), .CmpNV(CmpNVE), 
-               .CmpFpRes(CmpFpResE), .CmpIntRes(CmpIntResE));
+      .CmpFpRes(CmpFpResE), .CmpIntRes(CmpIntResE));
-   // sign injection
+
-   //    - fsgnj/fsgnjx/fsgnjn
+   // sign injection: fsgnj/fsgnjx/fsgnjn
    fsgninj fsgninj(.OpCtrl(OpCtrlE[1:0]), .Xs(XsE), .Ys(YsE), .X(XE), .Fmt(FmtE), .SgnRes(SgnResE));
 
-   // classify
+   // classify: fclass
-   //    - fclass
    fclassify fclassify (.Xs(XsE), .XSubnorm(XSubnormE), .XZero(XZeroE), .XNaN(XNaNE), 
-                        .XInf(XInfE), .XSNaN(XSNaNE), .ClassRes(ClassResE));
+      .XInf(XInfE), .XSNaN(XSNaNE), .ClassRes(ClassResE));
 
-   // convert
+   // convert: fcvt.*.*
-   //    - fcvt.*.*
    fcvt fcvt (.Xs(XsE), .Xe(XeE), .Xm(XmE), .Int(ForwardedSrcAE), .OpCtrl(OpCtrlE), 
-              .ToInt(FWriteIntE), .XZero(XZeroE), .Fmt(FmtE), .Ce(CeE), 
+      .ToInt(FWriteIntE), .XZero(XZeroE), .Fmt(FmtE), .Ce(CeE), .ShiftAmt(CvtShiftAmtE), 
-              .ShiftAmt(CvtShiftAmtE), .ResSubnormUf(CvtResSubnormUfE), .Cs(CsE), .IntZero(IntZeroE), 
+      .ResSubnormUf(CvtResSubnormUfE), .Cs(CsE), .IntZero(IntZeroE), .LzcIn(CvtLzcInE));
-              .LzcIn(CvtLzcInE));
 
-   // data to be stored in memory - to IEU
-   //    - FP uses NaN-blocking format
-   //        - if there are any unsused bits the most significant bits are filled with 1s
 
-   flopenrc #(`FLEN) FWriteDataMReg (clk, reset, FlushM, ~StallM, YE, FWriteDataM);
+   // NaN Box SrcA to convert integer to requested FP size
-
-   // NaN Block SrcA
    generate
    if(`FPSIZES == 1) assign AlignedSrcAE = {{`FLEN-`XLEN{1'b1}}, ForwardedSrcAE};
    else if(`FPSIZES == 2) 
@@ -314,8 +284,6 @@ module fpu (
    assign PreNVE = CmpNVE&(OpCtrlE[2]|FWriteIntE);
 
    // select the result that may be written to the integer register - to IEU
-   
-   logic [`FLEN-1:0] SgnExtXE;
    generate
    if(`FPSIZES == 1)
       assign SgnExtXE = XE;
@@ -325,20 +293,18 @@ module fpu (
       mux4 #(`FLEN) fmulzeromux ({{`FLEN-`H_LEN{XsE}}, XE[`H_LEN-1:0]}, 
                                  {{`FLEN-`S_LEN{XsE}}, XE[`S_LEN-1:0]}, 
                                  {{`FLEN-`D_LEN{XsE}}, XE[`D_LEN-1:0]}, 
-                                 XE, FmtE, SgnExtXE); // NaN boxing zeroes
+                                 XE, FmtE, SgnExtXE); 
    endgenerate
    if (`FLEN>`XLEN)
       assign IntSrcXE = SgnExtXE[`XLEN-1:0];
    else 
       assign IntSrcXE = {{`XLEN-`FLEN{XsE}}, SgnExtXE};
-
    mux3 #(`XLEN) IntResMux (ClassResE, IntSrcXE, CmpIntResE, {~FResSelE[1], FResSelE[0]}, FIntResE);
-   // *** DH 5/25/22: CvtRes will move to mem stage.  Premux in execute to save area, then make sure stalls are ok
-   // *** make sure the fpu matches the chapter diagram
 
    // E/M pipe registers
 
-   assign StallUnpackedM = StallM | (FDivBusyE & ~IFDivStartE | FDivDoneE); // Need to stall during divsqrt iterations to avoid capturing bad flags from stale forwarded sources
+   // Need to stall during divsqrt iterations to avoid capturing bad flags from stale forwarded sources
+   assign StallUnpackedM = StallM | (FDivBusyE & ~IFDivStartE | FDivDoneE); 
 
    flopenrc #(`NF+1) EMFpReg2 (clk, reset, FlushM, ~StallM, XmE, XmM);
    flopenrc #(`NF+1) EMFpReg3 (clk, reset, FlushM, ~StallM, YmE, YmM);
@@ -346,60 +312,44 @@ module fpu (
    flopenrc #(`XLEN) EMFpReg6 (clk, reset, FlushM, ~StallM, FIntResE, FIntResM);
    flopenrc #(`FLEN) EMFpReg7 (clk, reset, FlushM, ~StallM, PreFpResE, PreFpResM);
    flopenr #(13) EMFpReg5 (clk, reset, ~StallUnpackedM, 
-            {XsE, YsE, XZeroE, YZeroE, XInfE, YInfE, ZInfE, XNaNE, YNaNE, ZNaNE, XSNaNE, YSNaNE, ZSNaNE},
+      {XsE, YsE, XZeroE, YZeroE, XInfE, YInfE, ZInfE, XNaNE, YNaNE, ZNaNE, XSNaNE, YSNaNE, ZSNaNE},
-            {XsM, YsM, XZeroM, YZeroM, XInfM, YInfM, ZInfM, XNaNM, YNaNM, ZNaNM, XSNaNM, YSNaNM, ZSNaNM});     
+      {XsM, YsM, XZeroM, YZeroM, XInfM, YInfM, ZInfM, XNaNM, YNaNM, ZNaNM, XSNaNM, YSNaNM, ZSNaNM});     
    flopenrc #(1)  EMRegCmpFlg (clk, reset, FlushM, ~StallM, PreNVE, PreNVM);      
    flopenrc #(3*`NF+4) EMRegFma2(clk, reset, FlushM, ~StallM, SmE, SmM);
-  flopenrc #($clog2(3*`NF+5)+7+`NE) EMRegFma4(clk, reset, FlushM, ~StallM,
+   flopenrc #($clog2(3*`NF+5)+7+`NE) EMRegFma4(clk, reset, FlushM, ~StallM,
-                           {FmaAStickyE, InvAE, SCntE, AsE, PsE, SsE, SeE},
+      {FmaAStickyE, InvAE, SCntE, AsE, PsE, SsE, SeE},
-                           {FmaAStickyM, InvAM, SCntM, AsM, PsM, SsM, SeM});
+      {FmaAStickyM, InvAM, SCntM, AsM, PsM, SsM, SeM});
    flopenrc #(`NE+`LOGCVTLEN+`CVTLEN+4) EMRegCvt(clk, reset, FlushM, ~StallM, 
-                           {CeE, CvtShiftAmtE, CvtResSubnormUfE, CsE, IntZeroE, CvtLzcInE},
+      {CeE, CvtShiftAmtE, CvtResSubnormUfE, CsE, IntZeroE, CvtLzcInE},
-                           {CeM, CvtShiftAmtM, CvtResSubnormUfM, CsM, IntZeroM, CvtLzcInM});
+      {CeM, CvtShiftAmtM, CvtResSubnormUfM, CsM, IntZeroM, CvtLzcInM});
-
+   flopenrc #(`FLEN) FWriteDataMReg (clk, reset, FlushM, ~StallM, YE, FWriteDataM);
-   // BEGIN MEMORY STAGE
 
    //////////////////////////////////////////////////////////////////////////////////////////
-   //          |||         |||
+   // Memory Stage: postprocessor and result muxes
-   //          ||||||   ||||||
-   //          ||| ||| ||| |||
-   //          |||  |||||  |||
-   //          |||   |||   |||
-   //          |||         |||
-   //          |||         |||
    //////////////////////////////////////////////////////////////////////////////////////////
 
-   assign FpLoadStoreM = FResSelM[1];
-
    postprocess postprocess(.Xs(XsM), .Ys(YsM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM), 
-                           .FmaASticky(FmaAStickyM), .XZero(XZeroM), .YZero(YZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QmM), .FmaSs(SsM),
+      .FmaASticky(FmaAStickyM), .XZero(XZeroM), .YZero(YZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QmM), .FmaSs(SsM),
-                           .ZInf(ZInfM), .XNaN(XNaNM), .YNaN(YNaNM), .ZNaN(ZNaNM), .XSNaN(XSNaNM), .YSNaN(YSNaNM), .ZSNaN(ZSNaNM), .FmaSm(SmM), .DivQe(QeM), /*.DivDone(DivDoneM), */
+      .ZInf(ZInfM), .XNaN(XNaNM), .YNaN(YNaNM), .ZNaN(ZNaNM), .XSNaN(XSNaNM), .YSNaN(YSNaNM), .ZSNaN(ZSNaNM), 
-                           .FmaAs(AsM), .FmaPs(PsM), .OpCtrl(OpCtrlM), .FmaSCnt(SCntM), .FmaSe(SeM),
+      .FmaSm(SmM), .DivQe(QeM), .FmaAs(AsM), .FmaPs(PsM), .OpCtrl(OpCtrlM), .FmaSCnt(SCntM), .FmaSe(SeM),
-                           .CvtCe(CeM), .CvtResSubnormUf(CvtResSubnormUfM),.CvtShiftAmt(CvtShiftAmtM), .CvtCs(CsM), .ToInt(FWriteIntM), .DivS(DivSM),
+      .CvtCe(CeM), .CvtResSubnormUf(CvtResSubnormUfM),.CvtShiftAmt(CvtShiftAmtM), .CvtCs(CsM), 
-                           .CvtLzcIn(CvtLzcInM), .IntZero(IntZeroM), .PostProcSel(PostProcSelM), .PostProcRes(PostProcResM), .PostProcFlg(PostProcFlgM), .FCvtIntRes(FCvtIntResM));
+      .ToInt(FWriteIntM), .DivSticky(DivStickyM), .CvtLzcIn(CvtLzcInM), .IntZero(IntZeroM), 
+      .PostProcSel(PostProcSelM), .PostProcRes(PostProcResM), .PostProcFlg(PostProcFlgM), .FCvtIntRes(FCvtIntResM));
 
    // FPU flag selection - to privileged
-   mux2  #(5)  FPUFlgMux ({PreNVM&~FResSelM[1], 4'b0}, PostProcFlgM, ~FResSelM[1]&FResSelM[0], SetFflagsM);
+   mux2  #(5)      FPUFlgMux({PreNVM&~FResSelM[1], 4'b0}, PostProcFlgM, ~FResSelM[1]&FResSelM[0], SetFflagsM);
-   mux2  #(`FLEN)  FPUResMux (PreFpResM, PostProcResM, FResSelM[0], FpResM);
+   mux2  #(`FLEN)  FPUResMux(PreFpResM, PostProcResM, FResSelM[0], FpResM);
 
    // M/W pipe registers
    flopenrc #(`FLEN) MWRegFp(clk, reset, FlushW, ~StallW, FpResM, FpResW); 
    flopenrc #(`XLEN) MWRegIntCvtRes(clk, reset, FlushW, ~StallW, FCvtIntResM, FCvtIntResW); 
-   flopenrc #(`XLEN) MWRegIntDivRes(clk, reset, FlushW, ~StallW, FPIntDivResultM, FPIntDivResultW); 
+   flopenrc #(`XLEN) MWRegIntDivRes(clk, reset, FlushW, ~StallW, FIntDivResultM, FIntDivResultW); 
-
-   // BEGIN WRITEBACK STAGE
 
    //////////////////////////////////////////////////////////////////////////////////////////
-   //         |||           |||
+   // Writeback Stage: result mux
-   //         |||           |||
-   //         |||    |||    |||
-   //         |||   |||||   |||
-   //         |||  ||| |||  |||
-   //          ||||||   ||||||
-   //          |||         |||
    //////////////////////////////////////////////////////////////////////////////////////////
 
    // select the result to be written to the FP register
-   mux2  #(`FLEN)  FPUResultMux (FpResW, ReadDataW, FResSelW[1], FPUResultW);
+   mux2  #(`FLEN)  FResultMux (FpResW, ReadDataW, FResSelW[1], FResultW);
 
 endmodule // fpu

pipelined/src/fpu/fregfile.sv

@@ -4,41 +4,40 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: James Stine 
 //
-// Purpose: 3-port output register file
+// Purpose: 3R1W 4-port register file for FPU
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
 
 module fregfile (
-  input logic 	      clk, reset,
+  input logic 	           clk, reset,
-  input logic 	      we4, 
+  input logic 	           we4,             // write enable
-  input logic [4:0]   a1, a2, a3, a4, 
+  input logic [4:0]        a1, a2, a3, a4,  // adresses
-  input logic [`FLEN-1:0]  wd4,
+  input logic [`FLEN-1:0]  wd4,             // write data
-  output logic [`FLEN-1:0] rd1, rd2, rd3);
+  output logic [`FLEN-1:0] rd1, rd2, rd3    // read data
+);
    
-   logic [`FLEN-1:0]       rf[31:0];
+   logic [`FLEN-1:0] rf[31:0];
-   integer 	      i;
+   integer i;
    
    // three ported register file
    // read three ports combinationally (A1/RD1, A2/RD2, A3/RD3)

pipelined/src/fpu/fsgninj.sv

@@ -6,39 +6,37 @@
 //
 // Purpose: FPU Sign Injection instructions
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
 
 module fsgninj (  
-	input logic        			Xs, Ys,	// X and Y sign bits
+	input  logic        		Xs, Ys,	// X and Y sign bits
-	input logic [`FLEN-1:0] 	X,		// X
+	input  logic [`FLEN-1:0] 	X,		// X
-	input logic [`FMTBITS-1:0]	Fmt,	// format
+	input  logic [`FMTBITS-1:0]	Fmt,	// format
 	input  logic [1:0]  		OpCtrl,	// operation control
 	output logic [`FLEN-1:0] 	SgnRes	// result
 );
 
-	logic ResSgn;
+	logic ResSgn;	// result sign
 
 	// OpCtrl:
 	// 		00 - fsgnj  - directly copy over sign value of Y

pipelined/src/fpu/postproc/cvtshiftcalc.sv

@@ -6,42 +6,41 @@
 //
 // Purpose: Conversion shift calculation
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
+
 `include "wally-config.vh"
 
 module cvtshiftcalc(
-    input logic                     XZero,      // is the input zero?
+    input  logic                    XZero,              // is the input zero?
-    input logic                     ToInt,      // to integer conversion?
+    input  logic                    ToInt,              // to integer conversion?
-    input logic                     IntToFp,    // interger to floating point conversion?
+    input  logic                    IntToFp,            // interger to floating point conversion?
-    input logic  [`NE:0]            CvtCe,      // the calculated expoent
+    input  logic [`FMTBITS-1:0]     OutFmt,             // output format
-    input logic  [`NF:0]            Xm,         // input mantissas
+    input  logic [`NE:0]            CvtCe,              // the calculated expoent
-    input logic  [`FMTBITS-1:0]     OutFmt,     // output format
+    input  logic [`NF:0]            Xm,                 // input mantissas
-    input logic  [`CVTLEN-1:0]      CvtLzcIn,   // input to the Leading Zero Counter (priority encoder)
+    input  logic [`CVTLEN-1:0]      CvtLzcIn,           // input to the Leading Zero Counter (without msb)
-    input logic                     CvtResSubnormUf, // is the conversion result subnormal or underlows
+    input  logic                    CvtResSubnormUf,    // is the conversion result subnormal or underlows
-    output logic                    CvtResUf,       // does the cvt result unerflow
+    output logic                    CvtResUf,           // does the cvt result unerflow
-    output logic [`CVTLEN+`NF:0]    CvtShiftIn      // number to be shifted
+    output logic [`CVTLEN+`NF:0]    CvtShiftIn          // number to be shifted
 );
-    logic [$clog2(`NF):0]	ResNegNF;   // the result's fraction length negated (-NF)
+    logic [$clog2(`NF):0] ResNegNF; // the result's fraction length negated (-NF)
 
 
     ///////////////////////////////////////////////////////////////////////////
@@ -50,23 +49,24 @@ module cvtshiftcalc(
 
     // seclect the input to the shifter
     //      fp  -> int:
-    //          |  `XLEN  zeros |     Mantissa      | 0's if nessisary |
+    //          |  `XLEN  zeros |     mantissa      | 0's if nessisary |
     //                          .
     //          Other problems:
     //              - if shifting to the right (neg CalcExp) then don't a 1 in the round bit (to prevent an incorrect plus 1 later durring rounding)
     //              - we do however want to keep the one in the sticky bit so set one of bits in the sticky bit area to 1
     //                  - ex: for the case 0010000.... (double)
     //      ??? -> fp:
-    //          - if result is Subnormalized or underflowed then we want to shift right i.e. shift right then shift left:
+    //          - if result is subnormal or underflowed then we want to shift right i.e. shift right then shift left:
-    //              |  `NF-1  zeros   |     Mantissa      | 0's if nessisary | 
+    //              |  `NF-1  zeros   |     mantissa      | 0's if nessisary | 
     //              .
     //          - otherwise:
     //              |     LzcInM      | 0's if nessisary | 
     //              .
     // change to int shift to the left one
-
+    always_comb 
-    always_comb //                                            get rid of round bit if needed
+    //                                                        get rid of round bit if needed
     //                                                        |                    add sticky bit if needed
+    //                                                        |                    |
         if (ToInt)               CvtShiftIn = {{`XLEN{1'b0}}, Xm[`NF]&~CvtCe[`NE], Xm[`NF-1]|(CvtCe[`NE]&Xm[`NF]), Xm[`NF-2:0], {`CVTLEN-`XLEN{1'b0}}};
         else if (CvtResSubnormUf) CvtShiftIn = {{`NF-1{1'b0}}, Xm, {`CVTLEN-`NF+1{1'b0}}};
         else                     CvtShiftIn = {CvtLzcIn, {`NF+1{1'b0}}};
@@ -96,6 +96,9 @@ module cvtshiftcalc(
                 2'h2: ResNegNF = -($clog2(`NF)+1)'(`H_NF);
             endcase
     end
+
+
+    
     // determine if the result underflows ??? -> fp
     //      - if the first 1 is shifted out of the result then the result underflows
     //      - can't underflow an integer to fp conversions

pipelined/src/fpu/postproc/divshiftcalc.sv

@@ -4,48 +4,47 @@
 // Written: me@KatherineParry.com
 // Modified: 7/5/2022
 //
-// Purpose: Conversion shift calculation
+// Purpose: Division shift calculation
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////`include "wally-config.vh"
 
 `include "wally-config.vh"
 
 module divshiftcalc(
-    input logic  [`DIVb:0] DivQm,
+    input  logic [`DIVb:0]              DivQm,              // divsqrt significand
-   input logic [`NE+1:0] DivQe,
+    input  logic [`NE+1:0]              DivQe,              // divsqrt exponent
-    output logic [`LOGNORMSHIFTSZ-1:0] DivShiftAmt,
+    output logic [`LOGNORMSHIFTSZ-1:0]  DivShiftAmt,        // divsqrt shift amount
-    output logic [`NORMSHIFTSZ-1:0] DivShiftIn,
+    output logic [`NORMSHIFTSZ-1:0]     DivShiftIn,         // divsqrt shift input
-    output logic DivResSubnorm,
+    output logic                        DivResSubnorm,      // is the divsqrt result subnormal
-    output logic DivSubnormShiftPos
+    output logic                        DivSubnormShiftPos  // is the subnormal shift amount positive
 );
-    logic [`LOGNORMSHIFTSZ-1:0] NormShift, DivSubnormShiftAmt;
+    logic [`LOGNORMSHIFTSZ-1:0] NormShift;          // normalized result shift amount
-    logic [`NE+1:0] DivSubnormShift;
+    logic [`LOGNORMSHIFTSZ-1:0] DivSubnormShiftAmt; // subnormal result shift amount (killed if negitive)
+    logic [`NE+1:0]             DivSubnormShift;    // subnormal result shift amount
  
-    // is the result Subnormalized
+    // is the result subnormal
     // if the exponent is 1 then the result needs to be normalized then the result is Subnormalizes
     assign DivResSubnorm = DivQe[`NE+1]|(~|DivQe[`NE+1:0]);
 
-    // if the result is Subnormalized
+    // if the result is subnormal
     //  00000000x.xxxxxx...                     Exp = DivQe
     //  .00000000xxxxxxx... >> NF+1             Exp = DivQe+NF+1
     //  .00xxxxxxxxxxxxx... << DivQe+NF+1  Exp = +1
@@ -69,5 +68,6 @@ module divshiftcalc(
     assign DivSubnormShiftAmt = DivSubnormShiftPos ? DivSubnormShift[`LOGNORMSHIFTSZ-1:0] : '0;
     assign DivShiftAmt = DivResSubnorm ? DivSubnormShiftAmt : NormShift;
 
+    // pre-shift the divider result for normalization
     assign DivShiftIn = {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb-1-`NF{1'b0}}};
 endmodule

pipelined/src/fpu/postproc/flags.sv

@@ -6,73 +6,92 @@
 //
 // Purpose: Post-Processing flag calculation
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 `include "wally-config.vh"
 
 module flags(
-    input logic                 Xs,
+    input  logic                Xs,                     // X sign
-    input logic                 XSNaN, YSNaN, ZSNaN, // inputs are signaling NaNs
+    input  logic [`FMTBITS-1:0] OutFmt,                 // output format
-    input logic                 XInf, YInf, ZInf,    // inputs are infinity
+    input  logic                InfIn,                  // is a Inf input being used
-    input logic                 Plus1,
+    input  logic                XInf, YInf, ZInf,       // inputs are infinity
-    input logic                 InfIn,                  // is a Inf input being used
+    input  logic                NaNIn,                  // is a NaN input being used
-    input logic                 NaNIn,                  // is a NaN input being used
+    input  logic                XSNaN, YSNaN, ZSNaN,    // inputs are signaling NaNs
-    input logic [`FMTBITS-1:0]  OutFmt,                 // output format
+    input  logic                XZero, YZero,           // inputs are zero
-    input logic                 XZero, YZero,         // inputs are zero
+    input  logic [`NE+1:0]      FullRe,                 // Re with bits to determine sign and overflow
-    input logic                 Sqrt,                   // Sqrt?
+    input  logic [`NE+1:0]      Me,                     // exponent of the normalized sum
-    input logic                 ToInt,                  // convert to integer
+    // rounding
-    input logic                 IntToFp,                // convert integer to floating point
+    input  logic                Plus1,                  // do you add one for rounding
-    input logic                 Int64,                  // convert to 64 bit integer
+    input  logic                Round, Guard, Sticky,   // bits used to determine rounding
-    input logic                 Signed,                 // convert to a signed integer
+    input  logic                UfPlus1,                // do you add one for rounding for the unbounded exponent result
-    input logic [`NE:0]         CvtCe,            // the calculated expoent - Cvt
+    // convert
-    input logic                 CvtOp,                  // conversion opperation?
+    input  logic                CvtOp,                  // conversion opperation?
-    input logic                 DivOp,                  // conversion opperation?
+    input  logic                ToInt,                  // convert to integer
-    input logic                 FmaOp,                  // Fma opperation?
+    input  logic                IntToFp,                // convert integer to floating point
-    input logic  [`NE+1:0]      FullRe,             // Re with bits to determine sign and overflow
+    input  logic                Int64,                  // convert to 64 bit integer
-    input logic  [`NE+1:0]      Me,               // exponent of the normalized sum
+    input  logic                Signed,                 // convert to a signed integer
-    input logic  [1:0]          CvtNegResMsbs,             // the negitive integer result's most significant bits
+    input  logic [`NE:0]        CvtCe,                  // the calculated expoent - Cvt
-    input logic                 FmaAs, FmaPs,        // the product and modified Z signs
+    input  logic [1:0]          CvtNegResMsbs,          // the negitive integer result's most significant bits
-    input logic                 Round, Guard, Sticky, UfPlus1, // bits used to determine rounding
+    // divsqrt
-    output logic                DivByZero,
+    input  logic                DivOp,                  // conversion opperation?
-    output logic                IntInvalid, Invalid, Overflow, // flags used to select the res
+    input  logic                Sqrt,                   // Sqrt?
-    output logic [4:0]          PostProcFlg // flags
+    // fma
+    input  logic                FmaOp,                  // Fma opperation?
+    input  logic                FmaAs, FmaPs,           // the product and modified Z signs
+    // flags
+    output logic                DivByZero,              // divide by zero flag
+    output logic                Overflow,               // overflow flag to select result
+    output logic                Invalid,                // invalid flag to select the result
+    output logic                IntInvalid,             // invalid integer result to select
+    output logic [4:0]          PostProcFlg             // flags
 );
-    logic               SigNaN;     // is an input a signaling NaN
+    logic               SigNaN;         // is an input a signaling NaN
-    logic               Inexact;    // inexact flag
+    logic               Inexact;        // final inexact flag
-    logic               FpInexact;  // floating point inexact flag
+    logic               FpInexact;      // floating point inexact flag
-    logic               IntInexact; // integer inexact flag
+    logic               IntInexact;     // integer inexact flag
-    logic               FmaInvalid; // integer invalid flag
+    logic               FmaInvalid;     // integer invalid flag
-    logic               DivInvalid; // integer invalid flag
+    logic               DivInvalid;     // integer invalid flag
-    logic               Underflow;   // Underflow flag
+    logic               Underflow;      // Underflow flag
-    logic               ResExpGteMax; // is the result greater than or equal to the maximum floating point expoent
+    logic               ResExpGteMax;   // is the result greater than or equal to the maximum floating point expoent
-    logic               ShiftGtIntSz; // is the shift greater than the the integer size (use Re to account for possible roundning "shift")
+    logic               ShiftGtIntSz;   // is the shift greater than the the integer size (use Re to account for possible roundning "shift")
 
     ///////////////////////////////////////////////////////////////////////////////
-    // Flags
+    // Overflow
     ///////////////////////////////////////////////////////////////////////////////
 
-
+    // determine if the result exponent is greater than or equal to the maximum exponent or 
-
+    // the shift amount is greater than the integers size (for cvt to int)
-   if (`FPSIZES == 1) begin
+    // ShiftGtIntSz calculation:  
+    //      a left shift of intlen+1 is still in range but any more than that is an overflow
+    //              inital: |      64 0's         |    XLEN     |
+    //                      |      64 0's         |    XLEN     | << 64
+    //                      |      XLEN           |    00000... |
+    //      65 = ...0 0 0 0   0 1 0 0   0 0 0 1
+    //          |     or      | |     or      |
+    //      33 = ...0 0 0 0   0 0 1 0   0 0 0 1
+    //          |     or        | |     or    |
+    //      larger or equal if:
+    //          - any of the bits after the most significan 1 is one
+    //          - the most signifcant in 65 or 33 is still a one in the number and
+    //            one of the later bits is one
+    if (`FPSIZES == 1) begin
         assign ResExpGteMax = &FullRe[`NE-1:0] | FullRe[`NE];
         assign ShiftGtIntSz = (|FullRe[`NE:7]|(FullRe[6]&~Int64)) | ((|FullRe[4:0]|(FullRe[5]&Int64))&((FullRe[5]&~Int64) | FullRe[6]&Int64));
 
@@ -98,39 +117,37 @@ module flags(
                 `S_FMT: ResExpGteMax = &FullRe[`S_NE-1:0] | (|FullRe[`Q_NE:`S_NE]);
                 `H_FMT: ResExpGteMax = &FullRe[`H_NE-1:0] | (|FullRe[`Q_NE:`H_NE]);
             endcase
-            // a left shift of intlen+1 is still in range but any more than that is an overflow
-            //           inital: |      64 0's         |    XLEN     |
-            //                   |      64 0's         |    XLEN     | << 64
-            //                   |      XLEN           |    00000... |
-            // 65 = ...0 0 0 0   0 1 0 0   0 0 0 1
-            //      |     or      | |     or      |
-            // 33 = ...0 0 0 0   0 0 1 0   0 0 0 1
-            //      |     or        | |     or    |
-            // larger or equal if:
-            //      - any of the bits after the most significan 1 is one
-            //      - the most signifcant in 65 or 33 is still a one in the number and
-            //        one of the later bits is one
             assign ShiftGtIntSz = (|FullRe[`Q_NE:7]|(FullRe[6]&~Int64)) | ((|FullRe[4:0]|(FullRe[5]&Int64))&((FullRe[5]&~Int64) | FullRe[6]&Int64));
     end
 
+
+    // calulate overflow flag:
     //                 if the result is greater than or equal to the max exponent(not taking into account sign)
     //                 |           and the exponent isn't negitive
     //                 |           |                   if the input isnt infinity or NaN
     //                 |           |                   |            
     assign Overflow = ResExpGteMax & ~FullRe[`NE+1]&~(InfIn|NaNIn|DivByZero);
 
-    // detecting tininess after rounding
+    ///////////////////////////////////////////////////////////////////////////////
+    // Underflow
+    ///////////////////////////////////////////////////////////////////////////////
+
+    // calculate underflow flag: detecting tininess after rounding
     //                  the exponent is negitive
-    //                  |                    the result is Subnormalized
+    //                  |                    the result is subnormal
     //                  |                    |                    the result is normal and rounded from a Subnorm
     //                  |                    |                    |                                      and if given an unbounded exponent the result does not round
     //                  |                    |                    |                                      |                     and if the result is not exact
     //                  |                    |                    |                                      |                     |               and if the input isnt infinity or NaN
     //                  |                    |                    |                                      |                     |               |
     assign Underflow = ((FullRe[`NE+1] | (FullRe == 0) | ((FullRe == 1) & (Me == 0) & ~(UfPlus1&Guard)))&(Round|Sticky|Guard))&~(InfIn|NaNIn|DivByZero|Invalid);
-   //assign Underflow = ((FullRe[`NE+1] | (FullRe == 0) | ((FullRe == 1) & (Me == 0) & ~(UfPlus1&Guard)))&(Round|Sticky|Guard))&~(InfIn|NaNIn|DivByZero|Invalid|XZero);
 
-    // Set Inexact flag if the res is diffrent from what would be outputed given infinite precision
+
+    ///////////////////////////////////////////////////////////////////////////////
+    // Inexact
+    ///////////////////////////////////////////////////////////////////////////////
+
+    // Set Inexact flag if the result is diffrent from what would be outputed given infinite precision
     //      - Don't set the underflow flag if an underflowed res isn't outputed
     assign FpInexact = (Sticky|Guard|Overflow|Round)&~(InfIn|NaNIn|DivByZero|Invalid);
     //assign FpInexact = (Sticky|Guard|Overflow|Round)&~(InfIn|NaNIn|DivByZero|Invalid|XZero);
@@ -143,11 +160,16 @@ module flags(
     // select the inexact flag to output
     assign Inexact = ToInt ? IntInexact : FpInexact;
 
+    ///////////////////////////////////////////////////////////////////////////////
+    // Invalid
+    ///////////////////////////////////////////////////////////////////////////////
+
     // Set Invalid flag for following cases:
     //   1) any input is a signaling NaN
     //   2) Inf - Inf (unless x or y is NaN)
     //   3) 0 * Inf
 
+    // invalid flag for integer result
     //                  if the input is NaN or infinity
     //                  |           if the integer res overflows (out of range) 
     //                  |           |                                  if the input was negitive but ouputing to a unsigned number
@@ -158,16 +180,30 @@ module flags(
     assign IntInvalid = NaNIn|InfIn|(ShiftGtIntSz&~FullRe[`NE+1])|((Xs&~Signed)&(~((CvtCe[`NE]|(~|CvtCe))&~Plus1)))|(CvtNegResMsbs[1]^CvtNegResMsbs[0]);
     //                                                                                                     |
     //                                                                                                     or when the positive res rounds up out of range
+    
     assign SigNaN = (XSNaN&~(IntToFp&CvtOp)) | (YSNaN&~CvtOp) | (ZSNaN&FmaOp);
+    
+    // invalid flag for fma
     assign FmaInvalid = ((XInf | YInf) & ZInf & (FmaPs ^ FmaAs) & ~NaNIn) | (XZero & YInf) | (YZero & XInf);
+    
+    //invalid flag for division
     assign DivInvalid = ((XInf & YInf) | (XZero & YZero))&~Sqrt | (Xs&Sqrt&~NaNIn&~XZero);
 
     assign Invalid = SigNaN | (FmaInvalid&FmaOp) | (DivInvalid&DivOp);
 
+    ///////////////////////////////////////////////////////////////////////////////
+    // Divide by Zero
+    ///////////////////////////////////////////////////////////////////////////////
+
     // if dividing by zero and not 0/0
     //  - don't set flag if an input is NaN or Inf(IEEE says has to be a finite numerator)
     assign DivByZero = YZero&DivOp&~Sqrt&~(XZero|NaNIn|InfIn);  
 
+
+    ///////////////////////////////////////////////////////////////////////////////
+    // final flags
+    ///////////////////////////////////////////////////////////////////////////////
+
     // Combine flags
     //      - to integer results do not set the underflow or overflow flags
     assign PostProcFlg = {Invalid|(IntInvalid&CvtOp&ToInt), DivByZero, Overflow&~(ToInt&CvtOp), Underflow&~(ToInt&CvtOp), Inexact};

pipelined/src/fpu/postproc/fmashiftcalc.sv

@@ -4,39 +4,38 @@
 // Written: me@KatherineParry.com
 // Modified: 7/5/2022
 //
-// Purpose: Fma shift calculation
+// Purpose: FMA shift calculation
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
+
 `include "wally-config.vh"
 
 module fmashiftcalc(
-    input logic  [3*`NF+3:0]            FmaSm,      // the positive sum
+    input  logic [`FMTBITS-1:0]         Fmt,            // precision 1 = double 0 = single
-    input logic  [$clog2(3*`NF+5)-1:0]  FmaSCnt,    // normalization shift count
+    input  logic [`NE+1:0]              FmaSe,          // sum's exponent
-    input logic  [`FMTBITS-1:0]         Fmt,        // precision 1 = double 0 = single
+    input  logic [3*`NF+3:0]            FmaSm,          // the positive sum
-    input logic  [`NE+1:0]              FmaSe,      // sum's exponent
+    input  logic [$clog2(3*`NF+5)-1:0]  FmaSCnt,        // normalization shift count
-    output logic [`NE+1:0]              NormSumExp, //*** add fma // exponent of the normalized sum not taking into account Subnormal or zero results
+    output logic [`NE+1:0]              NormSumExp,     // exponent of the normalized sum not taking into account Subnormal or zero results
-    output logic                        FmaSZero,   // is the result Subnormalized - calculated before LZA corection
+    output logic                        FmaSZero,       // is the result subnormal - calculated before LZA corection
-    output logic                        FmaPreResultSubnorm, // is the result Subnormalized - calculated before LZA corection
+    output logic                        FmaPreResultSubnorm, // is the result subnormal - calculated before LZA corection
     output logic [$clog2(3*`NF+5)-1:0]  FmaShiftAmt,    // normalization shift count
     output logic [3*`NF+5:0]            FmaShiftIn      // is the sum zero
 );
@@ -46,8 +45,10 @@ module fmashiftcalc(
     ///////////////////////////////////////////////////////////////////////////////
     // Normalization
     ///////////////////////////////////////////////////////////////////////////////
+
     // Determine if the sum is zero
     assign FmaSZero = ~(|FmaSm);
+
     // calculate the sum's exponent
     assign PreNormSumExp = FmaSe + {{`NE+2-$unsigned($clog2(3*`NF+5)){1'b1}}, ~FmaSCnt} + (`NE+2)'(`NF+3);
 
@@ -83,8 +84,7 @@ module fmashiftcalc(
 
     end
     
-    // determine if the result is Subnormalized
+    // determine if the result is subnormal: (NormSumExp <= 0) & (NormSumExp >= -FracLen) & ~FmaSZero
-    
     if (`FPSIZES == 1) begin
         logic Sum0LEZ, Sum0GEFL;
         assign Sum0LEZ  = PreNormSumExp[`NE+1] | ~|PreNormSumExp;
@@ -137,16 +137,8 @@ module fmashiftcalc(
 
     end
 
-    // 010. when should be 001.
-    //      - shift left one
-    //      - add one from exp
-    //      - if kill prod dont add to exp
-
-    // Determine if the result is Subnormal
-    // assign FmaPreResultSubnorm = $signed(NormSumExp)<=0 & ($signed(NormSumExp)>=$signed(-FracLen)) & ~FmaSZero;
-
     // set and calculate the shift input and amount
-    //  - shift once if killing a product and the result is Subnormalized
+    //  - shift once if killing a product and the result is subnormal
     assign FmaShiftIn = {2'b0, FmaSm};
     if (`FPSIZES == 1)
         assign FmaShiftAmt = FmaPreResultSubnorm ? FmaSe[$clog2(3*`NF+5)-1:0]+($clog2(3*`NF+5))'(`NF+2): FmaSCnt+1;

pipelined/src/fpu/postproc/negateintres.sv

@@ -6,49 +6,45 @@
 //
 // Purpose: Negate integer result
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 `include "wally-config.vh"
 
 module negateintres(
-    input logic         Xs,
+  input  logic                    Signed,         // is the integer input signed
-    input logic [`NORMSHIFTSZ-1:0]  Shifted,
+  input  logic                    Int64,          // is the integer input 64-bits
-    input logic         Signed,
+  input  logic                    Plus1,          // should one be added for rounding?
-    input logic         Int64,
+  input  logic                    Xs,             // X sign
-    input logic         Plus1,
+  input  logic [`NORMSHIFTSZ-1:0] Shifted,        // output from normalization shifter
-    output logic [1:0]          CvtNegResMsbs,
+  output logic [1:0]              CvtNegResMsbs,  // most signigficant bits of possibly negated result
-    output logic [`XLEN+1:0]    CvtNegRes
+  output logic [`XLEN+1:0]        CvtNegRes       // possibly negated integer result
 );
 
+  logic [`XLEN+1:0]               CvtPreRes;      // integer result with rounding
+  logic [2:0]                     CvtNegResMsbs3; // first three msbs of possibly negated result
     
-    // round and negate the positive res if needed
+  // round and negate the positive res if needed
-    assign CvtNegRes = Xs ? -({2'b0, Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`XLEN]}+{{`XLEN+1{1'b0}}, Plus1}) : {2'b0, Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`XLEN]}+{{`XLEN+1{1'b0}}, Plus1};
+  assign CvtPreRes =  {2'b0, Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`XLEN]}+{{`XLEN+1{1'b0}}, Plus1};
-    
+  mux2 #(`XLEN+2) resmux(CvtPreRes, -CvtPreRes, Xs, CvtNegRes);
-    always_comb
-        if(Signed)
-            if(Int64)   CvtNegResMsbs = CvtNegRes[`XLEN:`XLEN-1];
-            else        CvtNegResMsbs = CvtNegRes[32:31];
-        else
-            if(Int64)   CvtNegResMsbs = CvtNegRes[`XLEN+1:`XLEN];
-            else        CvtNegResMsbs = CvtNegRes[33:32];
     
+  // select 2 most significant bits
+  mux2 #(3) msb3mux(CvtNegRes[33:31], CvtNegRes[`XLEN+1:`XLEN-1], Int64, CvtNegResMsbs3);
+  mux2 #(2) msb2mux(CvtNegResMsbs3[2:1], CvtNegResMsbs3[1:0], Signed, CvtNegResMsbs);
 endmodule

pipelined/src/fpu/postproc/normshift.sv

@@ -6,31 +6,29 @@
 //
 // Purpose: normalization shifter
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 `include "wally-config.vh"
 
 
- // convert shift
+    // convert shift
     //      fp -> int: |  `XLEN  zeros |     Mantissa      | 0's if nessisary | << CalcExp
     //          process:
     //              - start - CalcExp = 1 + XExp - Largest Bias
@@ -45,7 +43,7 @@
     //                  |     keep          |
     //
     //      fp -> fp:
-    //          - if result is Subnormalized or underflowed:
+    //          - if result is subnormal or underflowed:
     //              |  `NF-1  zeros   |     Mantissa      | 0's if nessisary | << NF+CalcExp-1
     //          process:
     //             - start
@@ -58,17 +56,26 @@
     //                 |   0's  |     mantissa      |     0's      |
     //                 |       keep      |
     //
-    //          - if the input is Subnormalized:
+    //          - if the input is subnormal:
     //              |     lzcIn      | 0's if nessisary | << ZeroCnt+1
     //              - plus 1 to shift out the first 1
     //
     //      int -> fp: |     lzcIn      | 0's if nessisary | << ZeroCnt+1
     //              - plus 1 to shift out the first 1
 
+    // fma shift
+    //      | 00 |           Sm           | << LZA output
+    //             .
+    //      - two extra bits so we can correct for an LZA error of 1 or 2
+
+    // divsqrt shift
+    //      | Nf 0's |      Qm       | << calculated shift amount
+    //        .
+
 module normshift(
-    input logic  [`LOGNORMSHIFTSZ-1:0]      ShiftAmt,   // normalization shift count
+    input  logic [`LOGNORMSHIFTSZ-1:0]  ShiftAmt,   // shift amount
-    input logic  [`NORMSHIFTSZ-1:0]              ShiftIn,        // is the sum zero
+    input  logic [`NORMSHIFTSZ-1:0]     ShiftIn,    // number to be shifted
-    output logic [`NORMSHIFTSZ-1:0]             Shifted        // is the sum zero
+    output logic [`NORMSHIFTSZ-1:0]     Shifted     // shifted result
 );
     assign Shifted = ShiftIn << ShiftAmt;
 

pipelined/src/fpu/postproc/postprocess.sv

@@ -4,28 +4,26 @@
 // Written: me@KatherineParry.com
 // Modified: 7/5/2022
 //
-// Purpose: Post-Processing
+// Purpose: Post-Processing: normalization, rounding, sign, flags, special cases
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
@@ -37,83 +35,85 @@ module postprocess (
     input logic  [2:0]                      Frm,        // rounding mode 000 = rount to nearest, ties to even   001 = round twords zero  010 = round down  011 = round up  100 = round to nearest, ties to max magnitude
     input logic  [`FMTBITS-1:0]             Fmt,        // precision 1 = double 0 = single
     input logic  [2:0]                      OpCtrl,     // choose which opperation (look below for values)
-    input logic                             XZero, YZero, // inputs are zero
+    input logic                             XZero, YZero,        // inputs are zero
     input logic                             XInf, YInf, ZInf,    // inputs are infinity
     input logic                             XNaN, YNaN, ZNaN,    // inputs are NaN
     input logic                             XSNaN, YSNaN, ZSNaN, // inputs are signaling NaNs
-    input logic  [1:0]                      PostProcSel,    // select result to be written to fp register
+    input logic  [1:0]                      PostProcSel,         // select result to be written to fp register
     //fma signals
-    input logic                             FmaAs,  // the modified Z sign - depends on instruction
+    input logic                             FmaAs,      // the modified Z sign - depends on instruction
-    input logic                             FmaPs,  // the product's sign
+    input logic                             FmaPs,      // the product's sign
-    input logic  [`NE+1:0]                  FmaSe,  // the sum's exponent
+    input logic                             FmaSs,      // Sum sign
-    input logic  [3*`NF+3:0]                FmaSm,  // the positive sum
+    input logic  [`NE+1:0]                  FmaSe,      // the sum's exponent
+    input logic  [3*`NF+3:0]                FmaSm,      // the positive sum
     input logic                             FmaASticky, // sticky bit that is calculated during alignment
-    input logic                             FmaSs,  //
+    input logic  [$clog2(3*`NF+5)-1:0]      FmaSCnt,    // the normalization shift count
-    input logic  [$clog2(3*`NF+5)-1:0]      FmaSCnt,   // the normalization shift count
     //divide signals
-    input logic                             DivS,
+    input logic                             DivSticky,  // divider sticky bit
-    input logic  [`NE+1:0]                  DivQe,
+    input logic  [`NE+1:0]                  DivQe,      // divsqrt exponent
-    input logic  [`DIVb:0]                  DivQm,
+    input logic  [`DIVb:0]                  DivQm,      // divsqrt significand
     // conversion signals
-    input logic                             CvtCs,     // the result's sign
+    input logic                             CvtCs,      // the result's sign
-    input logic  [`NE:0]                    CvtCe,    // the calculated expoent
+    input logic  [`NE:0]                    CvtCe,      // the calculated expoent
-    input logic                             CvtResSubnormUf,
+    input logic                             CvtResSubnormUf, // the convert result is subnormal or underflows
-	input logic  [`LOGCVTLEN-1:0]           CvtShiftAmt,  // how much to shift by
+	input logic  [`LOGCVTLEN-1:0]           CvtShiftAmt,// how much to shift by
-    input logic                             ToInt,     // is fp->int (since it's writting to the integer register)
+    input logic                             ToInt,      // is fp->int (since it's writting to the integer register)
-    input logic  [`CVTLEN-1:0]              CvtLzcIn,      // input to the Leading Zero Counter (priority encoder)
+    input logic  [`CVTLEN-1:0]              CvtLzcIn,   // input to the Leading Zero Counter (without msb)
-    input logic                             IntZero,         // is the input zero
+    input logic                             IntZero,    // is the integer input zero
     // final results
-    output logic [`FLEN-1:0]                PostProcRes,    // FMA final result
+    output logic [`FLEN-1:0]                PostProcRes,// postprocessor final result
-    output logic [4:0]                      PostProcFlg,
+    output logic [4:0]                      PostProcFlg,// postprocesser flags
-    output logic [`XLEN-1:0]                FCvtIntRes    // the int conversion result
+    output logic [`XLEN-1:0]                FCvtIntRes  // the integer conversion result
     );
    
     // general signals
-    logic Rs;
+    logic                       Rs;         // result sign
-    logic [`NF-1:0] Rf; // Result fraction
+    logic [`NF-1:0]             Rf;         // Result fraction
-    logic [`NE-1:0] Re;  // Result exponent
+    logic [`NE-1:0]             Re;         // Result exponent
-    logic Ms;
+    logic                       Ms;         // norMalized sign
-    logic [`NE+1:0] Me;
+    logic [`CORRSHIFTSZ-1:0]    Mf;         // norMalized fraction
-    logic [`CORRSHIFTSZ-1:0] Mf; // corectly shifted fraction
+    logic [`NE+1:0]             Me;         // normalized exponent
-    logic [`NE+1:0] FullRe;  // Re with bits to determine sign and overflow
+    logic [`NE+1:0]             FullRe;     // Re with bits to determine sign and overflow
-    logic UfPlus1;                    // do you add one (for determining underflow flag)
+    logic                       UfPlus1;    // do you add one (for determining underflow flag)
-    logic [`LOGNORMSHIFTSZ-1:0] ShiftAmt;   // normalization shift count
+    logic [`LOGNORMSHIFTSZ-1:0] ShiftAmt;   // normalization shift amount
-    logic [`NORMSHIFTSZ-1:0] ShiftIn;        // is the sum zero
+    logic [`NORMSHIFTSZ-1:0]    ShiftIn;    // input to normalization shift
-    logic [`NORMSHIFTSZ-1:0] Shifted;    // the shifted result
+    logic [`NORMSHIFTSZ-1:0]    Shifted;    // the ouput of the normalized shifter (before shift correction)
-    logic Plus1;      // add one to the final result?
+    logic                       Plus1;      // add one to the final result?
-    logic IntInvalid, Overflow, Invalid; // flags
+    logic                       Overflow;   // overflow flag used to select results
-    logic Guard, Round, Sticky; // bits needed to determine rounding
+    logic                       Invalid;    // invalid flag used to select results
-    logic [`FMTBITS-1:0] OutFmt;
+    logic                       Guard, Round, Sticky; // bits needed to determine rounding
+    logic [`FMTBITS-1:0]        OutFmt;     // output format
     // fma signals
-    logic [`NE+1:0] FmaMe;     // exponent of the normalized sum
+    logic [`NE+1:0]             FmaMe;      // exponent of the normalized sum
-    logic FmaSZero;        // is the sum zero
+    logic                       FmaSZero;   // is the sum zero
-    logic [3*`NF+5:0] FmaShiftIn;        // shift input
+    logic [3*`NF+5:0]           FmaShiftIn; // fma shift input
-    logic [`NE+1:0] NormSumExp;          // exponent of the normalized sum not taking into account Subnormal or zero results
+    logic [`NE+1:0]             NormSumExp; // exponent of the normalized sum not taking into account Subnormal or zero results
-    logic FmaPreResultSubnorm;    // is the result Subnormalized - calculated before LZA corection
+    logic                       FmaPreResultSubnorm; // is the result subnormal - calculated before LZA corection
-    logic [$clog2(3*`NF+5)-1:0] FmaShiftAmt;   // normalization shift count
+    logic [$clog2(3*`NF+5)-1:0] FmaShiftAmt;// normalization shift amount for fma
     // division singals
-    logic [`LOGNORMSHIFTSZ-1:0] DivShiftAmt;
+    logic [`LOGNORMSHIFTSZ-1:0] DivShiftAmt;        // divsqrt shif amount
-    logic [`NORMSHIFTSZ-1:0] DivShiftIn;
+    logic [`NORMSHIFTSZ-1:0]    DivShiftIn;         // divsqrt shift input
-    logic [`NE+1:0] Qe;
+    logic [`NE+1:0]             Qe;                 // divsqrt corrected exponent after corretion shift
-    logic DivByZero;
+    logic                       DivByZero;          // divide by zero flag
-    logic DivResSubnorm;
+    logic                       DivResSubnorm;      // is the divsqrt result subnormal
-    logic DivSubnormShiftPos;
+    logic                       DivSubnormShiftPos; // is the divsqrt subnorm shift amout positive (not underflowed)
     // conversion signals
-    logic [`CVTLEN+`NF:0] CvtShiftIn;    // number to be shifted
+    logic [`CVTLEN+`NF:0]       CvtShiftIn;         // number to be shifted for converter
-    logic [1:0] CvtNegResMsbs;
+    logic [1:0]                 CvtNegResMsbs;      // most significant bits of possibly negated int result
-    logic [`XLEN+1:0]    CvtNegRes;
+    logic [`XLEN+1:0]           CvtNegRes;          // possibly negated integer result
-    logic CvtResUf;
+    logic                       CvtResUf;           // did the convert result underflow
+    logic                       IntInvalid;         // invalid integer flag
     // readability signals
-    logic Mult;       // multiply opperation
+    logic                       Mult;       // multiply opperation
-    logic Int64;      // is the integer 64 bits?
+    logic                       Sqrt;       // is the divsqrt opperation sqrt
-    logic Signed;     // is the opperation with a signed integer?
+    logic                       Int64;      // is the integer 64 bits?
-    logic IntToFp;       // is the opperation an int->fp conversion?
+    logic                       Signed;     // is the opperation with a signed integer?
-    logic CvtOp;
+    logic                       IntToFp;    // is the opperation an int->fp conversion?
-    logic FmaOp;
+    logic                       CvtOp;      // convertion opperation
-    logic DivOp;
+    logic                       FmaOp;      // fma opperation
-    logic InfIn;
+    logic                       DivOp;      // divider opperation
-    logic NaNIn;
+    logic                       InfIn;      // are any of the inputs infinity
-    logic Sqrt;
+    logic                       NaNIn;      // are any of the inputs NaN
 
     // signals to help readability
     assign Signed =  OpCtrl[0];
@@ -122,7 +122,7 @@ module postprocess (
     assign Mult = OpCtrl[2]&~OpCtrl[1]&~OpCtrl[0];
     assign CvtOp = (PostProcSel == 2'b00);
     assign FmaOp = (PostProcSel == 2'b10);
-    assign DivOp = (PostProcSel == 2'b01); // & DivDone;
+    assign DivOp = (PostProcSel == 2'b01);
     assign Sqrt =  OpCtrl[0];
 
     // is there an input of infinity or NaN being used
@@ -141,12 +141,16 @@ module postprocess (
     // Normalization
     ///////////////////////////////////////////////////////////////////////////////
 
+    // final claulations before shifting
     cvtshiftcalc cvtshiftcalc(.ToInt, .CvtCe, .CvtResSubnormUf, .Xm, .CvtLzcIn,  
-                              .XZero, .IntToFp, .OutFmt, .CvtResUf, .CvtShiftIn);
+        .XZero, .IntToFp, .OutFmt, .CvtResUf, .CvtShiftIn);
+
     fmashiftcalc fmashiftcalc(.FmaSm, .FmaSCnt, .Fmt, .NormSumExp, .FmaSe,
-                          .FmaSZero, .FmaPreResultSubnorm, .FmaShiftAmt, .FmaShiftIn);
+        .FmaSZero, .FmaPreResultSubnorm, .FmaShiftAmt, .FmaShiftIn);
+
     divshiftcalc divshiftcalc(.DivQe, .DivQm, .DivResSubnorm, .DivSubnormShiftPos, .DivShiftAmt, .DivShiftIn);
 
+    // select which unit's output to shift
     always_comb
         case(PostProcSel)
             2'b10: begin // fma
@@ -157,14 +161,9 @@ module postprocess (
                 ShiftAmt = {{`LOGNORMSHIFTSZ-$clog2(`CVTLEN+1){1'b0}}, CvtShiftAmt};
                 ShiftIn =  {CvtShiftIn, {`NORMSHIFTSZ-`CVTLEN-`NF-1{1'b0}}};
             end
-            2'b01: begin //div
+            2'b01: begin //divsqrt
-               /* if(DivDone) begin */
                     ShiftAmt = DivShiftAmt;
                     ShiftIn =  DivShiftIn;
-              /*  end else begin
-                    ShiftAmt = '0;
-                    ShiftIn =  '0;
-                end */
             end
             default: begin 
                 ShiftAmt = {`LOGNORMSHIFTSZ{1'bx}}; 
@@ -172,11 +171,12 @@ module postprocess (
             end
         endcase
     
+    // main normalization shift
     normshift normshift (.ShiftIn, .ShiftAmt, .Shifted);
 
+    // correct for LZA/divsqrt error
     shiftcorrection shiftcorrection(.FmaOp, .FmaPreResultSubnorm, .NormSumExp,
-                                .DivResSubnorm, .DivSubnormShiftPos, .DivOp, .DivQe,
+        .DivResSubnorm, .DivSubnormShiftPos, .DivOp, .DivQe, .Qe, .FmaSZero, .Shifted, .FmaMe, .Mf);
-                                .Qe, .FmaSZero, .Shifted, .FmaMe, .Mf);
 
     ///////////////////////////////////////////////////////////////////////////////
     // Rounding
@@ -188,20 +188,19 @@ module postprocess (
     // round to infinity
     // round to nearest max magnitude
 
-                          
+    // calulate result sign used in rounding unit
     roundsign roundsign(.FmaOp, .DivOp, .CvtOp, .Sqrt, .FmaSs, .Xs, .Ys, .CvtCs, .Ms);
 
     round round(.OutFmt, .Frm, .FmaASticky, .Plus1, .PostProcSel, .CvtCe, .Qe,
-                .Ms, .FmaMe, .FmaOp, .CvtOp, .CvtResSubnormUf, .Mf, .ToInt,  .CvtResUf,
+        .Ms, .FmaMe, .FmaOp, .CvtOp, .CvtResSubnormUf, .Mf, .ToInt,  .CvtResUf,
-                .DivS, //.DivDone,
+        .DivSticky, .DivOp, .UfPlus1, .FullRe, .Rf, .Re, .Sticky, .Round, .Guard, .Me);
-                .DivOp, .UfPlus1, .FullRe, .Rf, .Re, .Sticky, .Round, .Guard, .Me);
 
     ///////////////////////////////////////////////////////////////////////////////
     // Sign calculation
     ///////////////////////////////////////////////////////////////////////////////
 
     resultsign resultsign(.Frm, .FmaPs, .FmaAs, .Round, .Sticky, .Guard,
-                          .FmaOp, .ZInf, .InfIn, .FmaSZero, .Mult, .Ms, .Rs);
+        .FmaOp, .ZInf, .InfIn, .FmaSZero, .Mult, .Ms, .Rs);
 
     ///////////////////////////////////////////////////////////////////////////////
     // Flags
@@ -218,10 +217,10 @@ module postprocess (
     ///////////////////////////////////////////////////////////////////////////////
 
     negateintres negateintres(.Xs, .Shifted, .Signed, .Int64, .Plus1, .CvtNegResMsbs, .CvtNegRes);
+
     specialcase specialcase(.Xs, .Xm, .Ym, .Zm, .XZero, .IntInvalid,
         .IntZero, .Frm, .OutFmt, .XNaN, .YNaN, .ZNaN, .CvtResUf, 
         .NaNIn, .IntToFp, .Int64, .Signed, .CvtOp, .FmaOp, .Plus1, .Invalid, .Overflow, .InfIn, .CvtNegRes,
-        .XInf, .YInf, .DivOp,
+        .XInf, .YInf, .DivOp, .DivByZero, .FullRe, .CvtCe, .Rs, .Re, .Rf, .PostProcRes, .FCvtIntRes);
-        .DivByZero, .FullRe, .CvtCe, .Rs, .Re, .Rf, .PostProcRes, .FCvtIntRes);
 
 endmodule

pipelined/src/fpu/postproc/resultsign.sv

@@ -6,69 +6,72 @@
 //
 // Purpose: calculating the result's sign
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
+
 `include "wally-config.vh"
 
 module resultsign(
-    input logic [2:0]   Frm,
+    input  logic [2:0]  Frm,        // rounding mode
-    input logic         FmaPs, FmaAs,
+    input  logic        FmaOp,      // is the operation an Fma
-    input logic         ZInf,
+    input  logic        Mult,       // is the fma opperation multipy
-    input logic         InfIn,
+    input  logic        ZInf,       // is Z infinity
-    input logic         FmaOp,
+    input  logic        InfIn,      // are any of the inputs infinity
-    input logic         FmaSZero,
+    input  logic        FmaSZero,   // is the fma sum zero
-    input logic         Mult,
+    input  logic        Ms,         // normalized result sign
-    input logic         Round,
+    input  logic        FmaPs,      // product's sign
-    input logic         Sticky,
+    input  logic        FmaAs,      // aligned addend's sign
-    input logic         Guard,
+    input  logic        Guard,      // guard bit for rounding
-    input logic         Ms,
+    input  logic        Round,      // round bit for rounding
-    output logic        Rs
+    input  logic        Sticky,     // sticky bit for rounding
+    output logic        Rs          // result sign
 );
 
-    logic Zeros;
+    logic Zeros;    // zero result sign
-    logic Infs;
+    logic Infs;     // infinity result sign
 
-    // The IEEE754-2019 standard specifies: 
+    // determine the sign for a result of 0
+    //  The IEEE754-2019 standard specifies: 
     //      - the sign of an exact zero sum (with operands of diffrent signs) should be positive unless rounding toward negitive infinity
     //      - when the exact result of an FMA opperation is non-zero, but is zero due to rounding, use the sign of the exact result
     //      - if x = +0 or -0 then x+x=x and x-(-x)=x 
     //      - the sign of a product is the exclisive or or the opperand's signs
-    // Zero sign will only be selected if:
+    //  Zero sign will only be selected if:
     //      - P=Z and a cancelation occurs - exact zero
     //      - Z is zero and P is zero - exact zero
     //      - P is killed and Z is zero - Psgn
     //      - Z is killed and P is zero - impossible
-    // Zero sign calculation:
+    //  Zero sign calculation:
     //      - if a multiply opperation is done, then use the products sign(Ps)
     //      - if the zero sum is not exactly zero i.e. Round|Sticky use the sign of the exact result (which is the product's sign)
     //      - if an effective addition occurs (P+A or -P+-A or P--A) then use the product's sign
     assign Zeros = (FmaPs^FmaAs)&~(Round|Guard|Sticky)&~Mult ? Frm[1:0] == 2'b10 : FmaPs;
 
-
+    // determine the sign of an infinity result
-    // is the result negitive
+    //  is the result negitive
-    //  if p - z is the Sum negitive
+    //      if p - z is the Sum negitive
-    //  if -p + z is the Sum positive
+    //      if -p + z is the Sum positive
-    //  if -p - z then the Sum is negitive
+    //      if -p - z then the Sum is negitive
     assign Infs = ZInf ? FmaAs : FmaPs;
+
+    // select the result sign
     always_comb
         if(InfIn&FmaOp) Rs = Infs;
         else if(FmaSZero&FmaOp) Rs = Zeros;

pipelined/src/fpu/postproc/round.sv

@@ -6,28 +6,28 @@
 //
 // Purpose: Rounder
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
+
 `include "wally-config.vh"
+
 // what position is XLEN in?
 //  options: 
 //     1: XLEN > NF   > NF1
@@ -37,38 +37,45 @@
 `define XLENPOS ((`XLEN>`NF) ? 1 : (`XLEN>`NF1) ? 2 : 3)
 
 module round(
-    input logic  [`FMTBITS-1:0]     OutFmt,     // precision 1 = double 0 = single
+    input  logic [`FMTBITS-1:0]     OutFmt,             // output format
-    input logic  [2:0]              Frm,        // rounding mode
+    input  logic [2:0]              Frm,                // rounding mode
-    input logic                     FmaOp,      // is an fma opperation being done?
+    input  logic [1:0]              PostProcSel,        // select the postprocessor output
-    input logic                     DivOp,      // is a division opperation being done
+    input  logic                    Ms,                 // normalized sign
-    input logic                     CvtOp,      // is a convert opperation being done
+    input  logic [`CORRSHIFTSZ-1:0] Mf,                 // normalized fraction
-    input logic                     ToInt,      // is the cvt op a cvt to integer
+    // fma
-    input logic  [1:0]              PostProcSel,    // select the postprocessor output
+    input  logic                    FmaOp,              // is an fma opperation being done?
-    input logic                     CvtResSubnormUf, // is the cvt result subnormal or underflow
+    input  logic [`NE+1:0]          FmaMe,              // exponent of the normalized sum for fma
-    input logic                     CvtResUf,
+    input  logic                    FmaASticky,         // addend's sticky bit
-    input logic  [`CORRSHIFTSZ-1:0] Mf,
+    // divsqrt
-    input logic                     FmaASticky,  // addend's sticky bit
+    input  logic                    DivOp,              // is a division opperation being done
-    input logic  [`NE+1:0]          FmaMe,         // exponent of the normalized sum
+    input  logic                    DivSticky,          // divsqrt sticky bit
-    input logic                     Ms,      // the result's sign
+    input  logic [`NE+1:0]          Qe,                 // the divsqrt calculated expoent
-    input logic  [`NE:0]            CvtCe,    // the calculated expoent
+    // cvt
-    input logic  [`NE+1:0]          Qe,    // the calculated expoent
+    input  logic                    CvtOp,              // is a convert opperation being done
-    input logic                     DivS,             // sticky bit
+    input  logic                    ToInt,              // is the cvt op a cvt to integer
-    output logic                    UfPlus1,  // do you add or subtract on from the result
+    input  logic                    CvtResSubnormUf,    // is the cvt result subnormal or underflow
-    output logic [`NE+1:0]          FullRe,      // Re with bits to determine sign and overflow
+    input  logic                    CvtResUf,           // does the cvt result underflow
-    output logic [`NF-1:0]          Rf,         // Result fraction
+    input  logic [`NE:0]            CvtCe,              // the cvt calculated expoent
-    output logic [`NE-1:0]          Re,          // Result exponent
+    // outputs
+    output logic [`NE+1:0]          Me,                 // normalied fraction
+    output logic                    UfPlus1,            // do you add one to the result if given an unbounded exponent
+    output logic [`NE+1:0]          FullRe,             // Re with bits to determine sign and overflow
+    output logic [`NE-1:0]          Re,                 // Result exponent
+    output logic [`NF-1:0]          Rf,                 // Result fractionNormS
     output logic                    Sticky,             // sticky bit
-    output logic [`NE+1:0]          Me,
+    output logic                    Plus1,              // do you add one to the final result
-    output logic                    Plus1,
+    output logic                    Round, Guard        // bits needed to calculate rounding
-    output logic                    Round, Guard // bits needed to calculate rounding
 );
-    logic           UfCalcPlus1; 
+    logic           UfCalcPlus1;        // calculated plus one for unbounded exponent
-    logic           NormS;  // normalized sum's sticky bit
+    logic           NormSticky;         // normalized sum's sticky bit
-    logic [`NF-1:0] RoundFrac;
+    logic [`NF-1:0] RoundFrac;          // rounded fraction
-    logic           FpRes, IntRes;
+    logic           FpRes;              // is the result a floating point
-    logic           FpGuard, FpLsbRes, FpRound;
+    logic           IntRes;             // is the result an integer
-    logic           LsbRes; // lsb of result
+    logic           FpGuard, FpRound;   // floating point round/guard bits
-    logic           CalcPlus1, FpPlus1;
+    logic           FpLsbRes;           // least significant bit of floating point result
+    logic           LsbRes;             // lsb of result
+    logic           CalcPlus1;          // calculated plus1
+    logic           FpPlus1;            // do you add one to the fp result 
     logic [`FLEN:0] RoundAdd;           // how much to add to the result
 
     ///////////////////////////////////////////////////////////////////////////////
@@ -101,21 +108,23 @@ module round(
     //      11 - do nothing if a small number was supposed to subtracted (the sticky bit was set by the small number)
     //         - Plus 1 otherwise
 
+
+    // determine what format the final result is in: int or fp
     assign IntRes = CvtOp & ToInt;
     assign FpRes = ~IntRes;
 
     // sticky bit calculation
     if (`FPSIZES == 1) begin
 
-    //     1: XLEN > NF
+        //     1: XLEN > NF
-    //      |         XLEN          |
+        //      |         XLEN          |
-    //      |    NF     |1|1|
+        //      |    NF     |1|1|
-    //                     ^    ^ if floating point result
+        //                     ^    ^ if floating point result
-    //                     ^ if not an FMA result
+        //                     ^ if not an FMA result
-        if (`XLENPOS == 1)assign NormS = (|Mf[`CORRSHIFTSZ-`NF-2:`CORRSHIFTSZ-`XLEN-1]&FpRes) |
+        if (`XLENPOS == 1)assign NormSticky = (|Mf[`CORRSHIFTSZ-`NF-2:`CORRSHIFTSZ-`XLEN-1]&FpRes) |
                                                  (|Mf[`CORRSHIFTSZ-`XLEN-2:0]);
-    //     2: NF > XLEN
+        //     2: NF > XLEN
-        if (`XLENPOS == 2)assign NormS = (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`NF-1]&IntRes) |
+        if (`XLENPOS == 2)assign NormSticky = (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`NF-1]&IntRes) |
                                                  (|Mf[`CORRSHIFTSZ-`NF-2:0]);
 
     end else if (`FPSIZES == 2) begin
@@ -123,31 +132,31 @@ module round(
         // so half and single are always smaller then XLEN
 
         // 1: XLEN > NF   > NF1
-        if (`XLENPOS == 1) assign NormS = (|Mf[`CORRSHIFTSZ-`NF1-2:`CORRSHIFTSZ-`NF-1]&FpRes&~OutFmt) |
+        if (`XLENPOS == 1) assign NormSticky = (|Mf[`CORRSHIFTSZ-`NF1-2:`CORRSHIFTSZ-`NF-1]&FpRes&~OutFmt) |
                                                   (|Mf[`CORRSHIFTSZ-`NF-2:`CORRSHIFTSZ-`XLEN-1]&FpRes) |
                                                   (|Mf[`CORRSHIFTSZ-`XLEN-2:0]);
         // 2: NF   > XLEN > NF1
-        if (`XLENPOS == 2) assign NormS = (|Mf[`CORRSHIFTSZ-`NF1-2:`CORRSHIFTSZ-`XLEN-1]&FpRes&~OutFmt) | 
+        if (`XLENPOS == 2) assign NormSticky = (|Mf[`CORRSHIFTSZ-`NF1-2:`CORRSHIFTSZ-`XLEN-1]&FpRes&~OutFmt) | 
                                                   (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`NF-1]&(IntRes|~OutFmt)) |
                                                   (|Mf[`CORRSHIFTSZ-`NF-2:0]);
         // 3: NF   > NF1  > XLEN
-        if (`XLENPOS == 3) assign NormS = (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`NF1-1]&IntRes) |
+        if (`XLENPOS == 3) assign NormSticky = (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`NF1-1]&IntRes) |
                                                   (|Mf[`CORRSHIFTSZ-`NF1-2:`CORRSHIFTSZ-`NF-1]&(~OutFmt|IntRes)) |
                                                   (|Mf[`CORRSHIFTSZ-`NF-2:0]);
 
     end else if (`FPSIZES == 3) begin
         // 1: XLEN > NF   > NF1
-        if (`XLENPOS == 1) assign NormS = (|Mf[`CORRSHIFTSZ-`NF2-2:`CORRSHIFTSZ-`NF1-1]&FpRes&(OutFmt==`FMT1)) |
+        if (`XLENPOS == 1) assign NormSticky = (|Mf[`CORRSHIFTSZ-`NF2-2:`CORRSHIFTSZ-`NF1-1]&FpRes&(OutFmt==`FMT1)) |
                                                   (|Mf[`CORRSHIFTSZ-`NF1-2:`CORRSHIFTSZ-`NF-1]&FpRes&~(OutFmt==`FMT)) |
                                                   (|Mf[`CORRSHIFTSZ-`NF-2:`CORRSHIFTSZ-`XLEN-1]&FpRes) |
                                                   (|Mf[`CORRSHIFTSZ-`XLEN-2:0]);
         // 2: NF   > XLEN > NF1
-        if (`XLENPOS == 2) assign NormS = (|Mf[`CORRSHIFTSZ-`NF2-2:`CORRSHIFTSZ-`NF1-1]&FpRes&(OutFmt==`FMT1)) |
+        if (`XLENPOS == 2) assign NormSticky = (|Mf[`CORRSHIFTSZ-`NF2-2:`CORRSHIFTSZ-`NF1-1]&FpRes&(OutFmt==`FMT1)) |
                                                   (|Mf[`CORRSHIFTSZ-`NF1-2:`CORRSHIFTSZ-`XLEN-1]&FpRes&~(OutFmt==`FMT)) | 
                                                   (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`NF-1]&(IntRes|~(OutFmt==`FMT))) |
                                                   (|Mf[`CORRSHIFTSZ-`NF-2:0]);
         // 3: NF   > NF1  > XLEN
-        if (`XLENPOS == 3) assign NormS = (|Mf[`CORRSHIFTSZ-`NF2-2:`CORRSHIFTSZ-`XLEN-1]&FpRes&(OutFmt==`FMT1)) |
+        if (`XLENPOS == 3) assign NormSticky = (|Mf[`CORRSHIFTSZ-`NF2-2:`CORRSHIFTSZ-`XLEN-1]&FpRes&(OutFmt==`FMT1)) |
                                                   (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`NF1-1]&((OutFmt==`FMT1)|IntRes)) |
                                                   (|Mf[`CORRSHIFTSZ-`NF1-2:`CORRSHIFTSZ-`NF-1]&(~(OutFmt==`FMT)|IntRes)) |
                                                   (|Mf[`CORRSHIFTSZ-`NF-2:0]);
@@ -155,14 +164,14 @@ module round(
     end else if (`FPSIZES == 4) begin
         // Quad precision will always be greater than XLEN
         // 2: NF   > XLEN > NF1
-        if (`XLENPOS == 2) assign NormS = (|Mf[`CORRSHIFTSZ-`H_NF-2:`CORRSHIFTSZ-`S_NF-1]&FpRes&(OutFmt==`H_FMT)) |
+        if (`XLENPOS == 2) assign NormSticky = (|Mf[`CORRSHIFTSZ-`H_NF-2:`CORRSHIFTSZ-`S_NF-1]&FpRes&(OutFmt==`H_FMT)) |
                                                   (|Mf[`CORRSHIFTSZ-`S_NF-2:`CORRSHIFTSZ-`D_NF-1]&FpRes&((OutFmt==`S_FMT)|(OutFmt==`H_FMT))) | 
                                                   (|Mf[`CORRSHIFTSZ-`D_NF-2:`CORRSHIFTSZ-`XLEN-1]&FpRes&~(OutFmt==`Q_FMT)) | 
                                                   (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`Q_NF-1]&(~(OutFmt==`Q_FMT)|IntRes)) |
                                                   (|Mf[`CORRSHIFTSZ-`Q_NF-2:0]);
         // 3: NF   > NF1  > XLEN
         // The extra XLEN bit will be ored later when caculating the final sticky bit - the ufplus1 not needed for integer
-        if (`XLENPOS == 3) assign NormS = (|Mf[`CORRSHIFTSZ-`H_NF-2:`CORRSHIFTSZ-`S_NF-1]&FpRes&(OutFmt==`H_FMT)) |
+        if (`XLENPOS == 3) assign NormSticky = (|Mf[`CORRSHIFTSZ-`H_NF-2:`CORRSHIFTSZ-`S_NF-1]&FpRes&(OutFmt==`H_FMT)) |
                                                   (|Mf[`CORRSHIFTSZ-`S_NF-2:`CORRSHIFTSZ-`XLEN-1]&FpRes&((OutFmt==`S_FMT)|(OutFmt==`H_FMT))) |
                                                   (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`D_NF-1]&((OutFmt==`S_FMT)|(OutFmt==`H_FMT)|IntRes)) |
                                                   (|Mf[`CORRSHIFTSZ-`D_NF-2:`CORRSHIFTSZ-`Q_NF-1]&(~(OutFmt==`Q_FMT)|IntRes)) |
@@ -174,7 +183,10 @@ module round(
 
     // only add the Addend sticky if doing an FMA opperation
     //      - the shifter shifts too far left when there's an underflow (shifting out all possible sticky bits)
-    assign Sticky = FmaASticky&FmaOp | NormS | CvtResUf&CvtOp | FmaMe[`NE+1]&FmaOp | DivS&DivOp;
+    assign Sticky = FmaASticky&FmaOp | NormSticky | CvtResUf&CvtOp | FmaMe[`NE+1]&FmaOp | DivSticky&DivOp;
+    
+
+
 
     // determine round and LSB of the rounded value
     //      - underflow round bit is used to determint the underflow flag
@@ -270,7 +282,10 @@ module round(
     assign FpPlus1 = Plus1&~(ToInt&CvtOp);
     assign UfPlus1 = UfCalcPlus1 & (Sticky|Round);
 
-    // Compute rounded result
+
+
+
+    // place Plus1 into the proper position for the format
     if (`FPSIZES == 1) begin
         assign RoundAdd = {{`FLEN{1'b0}}, FpPlus1};
 
@@ -287,9 +302,14 @@ module round(
     end else if (`FPSIZES == 4)      
         assign RoundAdd = {(`Q_NE+1+`H_NF)'(0), FpPlus1&(OutFmt==`H_FMT), (`S_NF-`H_NF-1)'(0), FpPlus1&(OutFmt==`S_FMT), (`D_NF-`S_NF-1)'(0), FpPlus1&(OutFmt==`D_FMT), (`Q_NF-`D_NF-1)'(0), FpPlus1&(OutFmt==`Q_FMT)};
 
-    // determine the result to be roundned
+
+
+    // trim unneeded bits from fraction
     assign RoundFrac = Mf[`CORRSHIFTSZ-1:`CORRSHIFTSZ-`NF];
     
+
+
+    // select the exponent
     always_comb
         case(PostProcSel)
             2'b10: Me = FmaMe; // fma
@@ -299,6 +319,8 @@ module round(
             default: Me = '0; 
         endcase
 
+
+
     // round the result
     //      - if the fraction overflows one should be added to the exponent
     assign {FullRe, Rf} = {Me, RoundFrac} + RoundAdd;

pipelined/src/fpu/postproc/roundsign.sv

@@ -4,48 +4,47 @@
 // Written: me@KatherineParry.com
 // Modified: 7/5/2022
 //
-// Purpose: Sign calculation ofr rounding
+// Purpose: Sign calculation for rounding
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 `include "wally-config.vh"
 
 module roundsign(
-    input logic         Xs,
+    input logic         Xs,     // x sign
-    input logic         Ys,
+    input logic         Ys,     // y sign
-    input logic         Sqrt,
+    input logic         CvtCs,  // convert result sign
-    input logic         FmaOp,
+    input logic         FmaSs,  // fma sum sign
-    input logic         DivOp,
+    input logic         Sqrt,   // sqrt oppertion? (when using divsqrt unit)
-    input logic         CvtOp,
+    input logic         FmaOp,  // is fma opperation
-    input logic         CvtCs,
+    input logic         DivOp,  // is divsqrt opperation
-    input logic         FmaSs,
+    input logic         CvtOp,  // is cvt opperation
-    output logic        Ms
+    output logic        Ms      // normalized result sign
 );
 
-    logic Qs;
+    logic Qs;   // divsqrt result sign
 
+    // calculate divsqrt sign
     assign Qs = Xs^(Ys&~Sqrt);
 
-    // Sign for rounding calulation
+    // Select sign for rounding calulation
     assign Ms = (FmaSs&FmaOp) | (CvtCs&CvtOp) | (Qs&DivOp);
 
 endmodule

pipelined/src/fpu/postproc/shiftcorrection.sv

@@ -6,63 +6,83 @@
 //
 // Purpose: shift correction
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 `include "wally-config.vh"
 
 module shiftcorrection(
-    input logic  [`NORMSHIFTSZ-1:0] Shifted,         // the shifted sum before LZA correction
+    input logic  [`NORMSHIFTSZ-1:0] Shifted,                // the shifted sum before LZA correction
-    input logic                     FmaOp,
+    // divsqrt
-    input logic                     DivOp,
+    input logic                     DivOp,                  // is it a divsqrt opperation
-    input logic                     DivResSubnorm,
+    input logic                     DivResSubnorm,          // is the divsqrt result subnormal
-    input logic  [`NE+1:0]          DivQe,
+    input logic  [`NE+1:0]          DivQe,                  // the divsqrt result's exponent
-    input logic                     DivSubnormShiftPos,
+    input logic                     DivSubnormShiftPos,     // is the subnorm divider shift amount positive (ie not underflowed)
-    input logic  [`NE+1:0]          NormSumExp,          // exponent of the normalized sum not taking into account Subnormal or zero results
+    //fma
-    input logic                     FmaPreResultSubnorm,    // is the result Subnormalized - calculated before LZA corection
+    input logic                     FmaOp,                  // is it an fma opperation
+    input logic  [`NE+1:0]          NormSumExp,             // exponent of the normalized sum not taking into account Subnormal or zero results
+    input logic                     FmaPreResultSubnorm,    // is the result subnormal - calculated before LZA corection
     input logic                     FmaSZero,
-    output logic [`CORRSHIFTSZ-1:0] Mf,         // the shifted sum before LZA correction
+    // output
-    output logic [`NE+1:0]          Qe,
+    output logic [`NE+1:0]          FmaMe,                  // exponent of the normalized sum
-    output logic [`NE+1:0]          FmaMe         // exponent of the normalized sum
+    output logic [`CORRSHIFTSZ-1:0] Mf,                     // the shifted sum before LZA correction
+    output logic [`NE+1:0]          Qe                      // corrected exponent for divider
 );
-    logic [3*`NF+3:0]      CorrSumShifted;     // the shifted sum after LZA correction
+
-    logic [`CORRSHIFTSZ-1:0] CorrQmShifted;
+    logic [3*`NF+3:0]           CorrSumShifted;             // the shifted sum after LZA correction
-    logic                  ResSubnorm;    // is the result Subnormalized
+    logic [`CORRSHIFTSZ-1:0]    CorrQm0, CorrQm1;           // portions of Shifted to select for CorrQmShifted
-    logic                  LZAPlus1; // add one or two to the sum's exponent due to LZA correction
+    logic [`CORRSHIFTSZ-1:0]    CorrQmShifted;              // the shifted divsqrt result after one bit shift
+    logic                       ResSubnorm;                 // is the result Subnormal
+    logic                       LZAPlus1;                   // add one or two to the sum's exponent due to LZA correction
+    logic                       LeftShiftQm;                // should the divsqrt result be shifted one to the left
 
     // LZA correction
     assign LZAPlus1 = Shifted[`NORMSHIFTSZ-1];
-	// the only possible mantissa for a plus two is all zeroes - a one has to propigate all the way through a sum. so we can leave the bottom statement alone
+
-    assign CorrSumShifted =  LZAPlus1 ? Shifted[`NORMSHIFTSZ-2:1] : Shifted[`NORMSHIFTSZ-3:0];
+    // correct the shifting error caused by the LZA
-    //                        if the msb is 1 or the exponent was one, but the shifted quotent was < 1 (Subnorm)
+	//  - the only possible mantissa for a plus two is all zeroes 
-    assign CorrQmShifted = (LZAPlus1|(DivQe==1&~LZAPlus1)) ? Shifted[`NORMSHIFTSZ-2:`NORMSHIFTSZ-`CORRSHIFTSZ-1] : Shifted[`NORMSHIFTSZ-3:`NORMSHIFTSZ-`CORRSHIFTSZ-2];
+    //      - a one has to propigate all the way through a sum. so we can leave the bottom statement alone
-    // if the result of the divider was calculated to be Subnormalized, then the result was correctly normalized, so select the top shifted bits
+    mux2 #(`NORMSHIFTSZ-2) lzacorrmux(Shifted[`NORMSHIFTSZ-3:0], Shifted[`NORMSHIFTSZ-2:1], LZAPlus1, CorrSumShifted);
+
+    // correct the shifting of the divsqrt caused by producing a result in (2, .5] range
+    //    condition: if the msb is 1 or the exponent was one, but the shifted quotent was < 1 (Subnorm)
+    assign LeftShiftQm = (LZAPlus1|(DivQe==1&~LZAPlus1));
+    assign CorrQm0 = Shifted[`NORMSHIFTSZ-3:`NORMSHIFTSZ-`CORRSHIFTSZ-2];
+    assign CorrQm1 = Shifted[`NORMSHIFTSZ-2:`NORMSHIFTSZ-`CORRSHIFTSZ-1];
+    mux2 #(`CORRSHIFTSZ) divcorrmux(CorrQm0, CorrQm1, LeftShiftQm, CorrQmShifted);
+    
+    // if the result of the divider was calculated to be subnormal, then the result was correctly normalized, so select the top shifted bits
     always_comb
         if(FmaOp)                       Mf = {CorrSumShifted, {`CORRSHIFTSZ-(3*`NF+4){1'b0}}};
-        else if (DivOp&~DivResSubnorm)   Mf = CorrQmShifted;
+        else if (DivOp&~DivResSubnorm)  Mf = CorrQmShifted;
         else                            Mf = Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`CORRSHIFTSZ];
     // Determine sum's exponent
-    //                          if plus1                     If plus2                                      if said Subnorm but norm plus 1           if said Subnorm but norm plus 2
+    //  main exponent issues: 
-    assign FmaMe = (NormSumExp+{{`NE+1{1'b0}}, LZAPlus1} +{{`NE+1{1'b0}}, ~ResSubnorm&FmaPreResultSubnorm}) & {`NE+2{~(FmaSZero|ResSubnorm)}};
+    //      - LZA was one too large
-    // recalculate if the result is Subnormalized
+    //      - LZA was two too large
+    //      - if the result was calulated to be subnorm but it's norm and the LZA was off by 1
+    //      - if the result was calulated to be subnorm but it's norm and the LZA was off by 2
+    //                          if plus1                    If plus2                               kill if the result Zero or actually subnormal
+    //                          |                           |                                      |
+    assign FmaMe = (NormSumExp+{{`NE+1{1'b0}}, LZAPlus1} +{{`NE+1{1'b0}}, FmaPreResultSubnorm}) & {`NE+2{~(FmaSZero|ResSubnorm)}};
+    
+    // recalculate if the result is subnormal after LZA correction
     assign ResSubnorm = FmaPreResultSubnorm&~Shifted[`NORMSHIFTSZ-2]&~Shifted[`NORMSHIFTSZ-1];
 
     // the quotent is in the range [.5,2) if there is no early termination

pipelined/src/fpu/postproc/specialcase.sv

@@ -6,73 +6,83 @@
 //
 // Purpose: special case selection
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
 
 module specialcase(
-    input logic                 Xs,        // input signs
+    input  logic                Xs,         // X sign
-    input logic  [`NF:0]        Xm, Ym, Zm, // input mantissas
+    input  logic [`NF:0]        Xm, Ym, Zm, // input significand's
-    input logic                 XNaN, YNaN, ZNaN,    // inputs are NaN
+    input  logic                XNaN, YNaN, ZNaN, // are the inputs NaN
-    input logic  [2:0]          Frm,       // rounding mode 000 = rount to nearest, ties to even   001 = round twords zero  010 = round down  011 = round up  100 = round to nearest, ties to max magnitude
+    input  logic [2:0]          Frm,        // rounding mode
-    input logic  [`FMTBITS-1:0] OutFmt,       // output format
+    input  logic [`FMTBITS-1:0] OutFmt,     // output format
-    input logic                 InfIn,
+    input  logic                InfIn,      // are any inputs infinity
-    input logic                 NaNIn,
+    input  logic                NaNIn,      // are any input NaNs
-    input logic                 XInf, YInf,
+    input  logic                XInf, YInf, // are X or Y inifnity
-    input logic                 XZero,
+    input  logic                XZero,      // is X zero
-    input logic                 IntZero,
+    input  logic                Plus1,      // do you add one for rounding
-    input logic                 IntToFp,
+    input  logic                Rs,         // the result's sign
-    input logic                 Int64,
+    input  logic                Invalid, Overflow,  // flags to choose the result
-    input logic                 Signed,
+    input  logic [`NE-1:0]      Re,         // Result exponent
-    input logic                 CvtOp,
+    input  logic [`NE+1:0]      FullRe,     // Result full exponent
-    input logic                 DivOp,
+    input  logic [`NF-1:0]      Rf,         // Result fraction
-    input logic                 FmaOp,
+    // fma
-    input logic                 Plus1,
+    input  logic                FmaOp,      // is it a fma opperation
-    input logic                 DivByZero,
+    // divsqrt
-    input logic  [`NE:0]        CvtCe,    // the calculated expoent
+    input  logic                DivOp,      // is it a divsqrt opperation
-    input logic                 Rs,  // the res's sign
+    input  logic                DivByZero,  // divide by zero flag
-    input logic                 IntInvalid, Invalid, Overflow,  // flags
+    // cvt
-    input logic                 CvtResUf,
+    input  logic                CvtOp,      // is it a conversion opperation
-    input logic  [`NE-1:0]      Re,          // Res exponent
+    input  logic                IntZero,    // is the integer input zero
-    input logic  [`NE+1:0]      FullRe,          // Res exponent
+    input  logic                IntToFp,    // is cvt int -> fp opperation
-    input logic  [`NF-1:0]      Rf,         // Res fraction
+    input  logic                Int64,      // is the integer 64 bits
-    input logic  [`XLEN+1:0]    CvtNegRes,     // the negation of the result
+    input  logic                Signed,     // is the integer signed
-    output logic [`FLEN-1:0]    PostProcRes,     // final res
+    input  logic [`NE:0]        CvtCe,      // the calculated expoent for cvt
-    output logic [`XLEN-1:0]    FCvtIntRes     // final res
+    input  logic                IntInvalid, // integer invalid flag to choose the result
+    input  logic                CvtResUf,   // does the convert result underflow
+    input  logic [`XLEN+1:0]    CvtNegRes,  // the possibly negated of the integer result
+    // outputs
+    output logic [`FLEN-1:0]    PostProcRes,// final result
+    output logic [`XLEN-1:0]    FCvtIntRes  // final integer result
 );
-    logic [`FLEN-1:0]   XNaNRes, YNaNRes, ZNaNRes, InvalidRes, OfRes, UfRes, NormRes; // possible results
+    logic [`FLEN-1:0]   XNaNRes;    // X is NaN result
-    logic OfResMax;
+    logic [`FLEN-1:0]   YNaNRes;    // Y is NaN result
-    logic [`XLEN-1:0]       OfIntRes;   // the overflow result for integer output
+    logic [`FLEN-1:0]   ZNaNRes;    // Z is NaN result
-    logic KillRes;
+    logic [`FLEN-1:0]   InvalidRes; // Invalid result result
-    logic SelOfRes;
+    logic [`FLEN-1:0]   UfRes;      // underflowed result result
+    logic [`FLEN-1:0]   OfRes;      // overflowed result result
+    logic [`FLEN-1:0]   NormRes;    // normal result
+    logic [`XLEN-1:0]   OfIntRes;   // the overflow result for integer output
+    logic               OfResMax;   // does the of result output maximum norm fp number
+    logic               KillRes;    // kill the result for underflow
+    logic               SelOfRes;   // should the overflow result be selected
 
 
     // does the overflow result output the maximum normalized floating point number
     //                output infinity if the input is infinity
     assign OfResMax = (~InfIn|(IntToFp&CvtOp))&~DivByZero&((Frm[1:0]==2'b01) | (Frm[1:0]==2'b10&~Rs) | (Frm[1:0]==2'b11&Rs));
 
-    if (`FPSIZES == 1) begin
 
+    // select correct outputs for special cases
+    if (`FPSIZES == 1) begin
         //NaN res selection depending on standard
         if(`IEEE754) begin
             assign XNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]};
@@ -87,7 +97,7 @@ module specialcase(
         assign UfRes = {Rs, {`FLEN-2{1'b0}}, Plus1&Frm[1]&~(DivOp&YInf)};
         assign NormRes = {Rs, Re, Rf};
 
-    end else if (`FPSIZES == 2) begin //will the format conversion in killprod work in other conversions?
+    end else if (`FPSIZES == 2) begin
         if(`IEEE754) begin
             assign XNaNRes = OutFmt ? {1'b0, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, Xm[`NF-2:`NF-`NF1]};
             assign YNaNRes = OutFmt ? {1'b0, {`NE{1'b1}}, 1'b1, Ym[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, Ym[`NF-2:`NF-`NF1]};
@@ -221,12 +231,11 @@ module specialcase(
                     end
                     
                     OfRes = OfResMax ? {{`FLEN-`H_LEN{1'b1}}, Rs, {`H_NE-1{1'b1}}, 1'b0, {`H_NF{1'b1}}} : {{`FLEN-`H_LEN{1'b1}}, Rs, {`H_NE{1'b1}}, (`H_NF)'(0)};      
-	            // zero is exact fi dividing by infinity so don't add 1
+	                // zero is exact if dividing by infinity so don't add 1
                     UfRes = {{`FLEN-`H_LEN{1'b1}}, Rs, (`H_LEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)};
                     NormRes = {{`FLEN-`H_LEN{1'b1}}, Rs, Re[`H_NE-1:0], Rf[`NF-1:`NF-`H_NF]};
                 end
             endcase
-
     end
 
     
@@ -238,7 +247,11 @@ module specialcase(
     //      - dont set to zero if fp input is zero but not using the fp input
     //      - dont set to zero if int input is zero but not using the int input
     assign KillRes = CvtOp ? (CvtResUf|(XZero&~IntToFp)|(IntZero&IntToFp)) : FullRe[`NE+1] | (((YInf&~XInf)|XZero)&DivOp);//Underflow & ~ResSubnorm & (Re!=1);
+    
+    // calculate if the overflow result should be selected
     assign SelOfRes = Overflow|DivByZero|(InfIn&~(YInf&DivOp));
+    
+    
     // output infinity with result sign if divide by zero
     if(`IEEE754)
         always_comb
@@ -256,17 +269,15 @@ module specialcase(
             else if(KillRes)            PostProcRes = UfRes;
             else                        PostProcRes = NormRes;
 
+
+
+
+
+
     ///////////////////////////////////////////////////////////////////////////////////////
-    //
+    // integer result selection        
-    //      |||||||||||   |||     |||   |||||||||||||
-    //          |||       ||||||  |||        |||
-    //          |||       ||| ||| |||        |||
-    //          |||       |||  ||||||        |||
-    //      |||||||||||   |||     |||        |||
-    //
     ///////////////////////////////////////////////////////////////////////////////////////        
 
-    // *** probably can optimize the negation
     // select the overflow integer res
     //      - negitive infinity and out of range negitive input
     //                 |  int  |  long  |

pipelined/src/fpu/unpack.sv

@@ -4,49 +4,47 @@
 // Written: me@KatherineParry.com
 // Modified: 7/5/2022
 //
-// Purpose: unpack all inputs
+// Purpose: unpack X, Y, Z floating-point inputs
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 `include "wally-config.vh"
 
 module unpack ( 
-    input logic  [`FLEN-1:0]        X, Y, Z,    // inputs from register file
+    input  logic [`FLEN-1:0]        X, Y, Z,        // inputs from register file
-    input logic  [`FMTBITS-1:0]     Fmt,       // format signal 00 - single 01 - double 11 - quad 10 - half
+    input  logic [`FMTBITS-1:0]     Fmt,            // format signal 00 - single 01 - double 11 - quad 10 - half
-    input logic                     XEn, YEn, ZEn,
+    input  logic                    XEn, YEn, ZEn,  // input enables
-    output logic                    Xs, Ys, Zs,    // sign bits of XYZ
+    output logic                    Xs, Ys, Zs,     // sign bits of XYZ
-    output logic [`NE-1:0]          Xe, Ye, Ze,    // exponents of XYZ (converted to largest supported precision)
+    output logic [`NE-1:0]          Xe, Ye, Ze,     // exponents of XYZ (converted to largest supported precision)
-    output logic [`NF:0]            Xm, Ym, Zm,    // mantissas of XYZ (converted to largest supported precision)
+    output logic [`NF:0]            Xm, Ym, Zm,     // mantissas of XYZ (converted to largest supported precision)
     output logic                    XNaN, YNaN, ZNaN,    // is XYZ a NaN
     output logic                    XSNaN, YSNaN, ZSNaN, // is XYZ a signaling NaN
-    output logic                    XSubnorm,   // is X Subnormalized
+    output logic                    XSubnorm,            // is X subnormal
-    output logic                    XZero, YZero, ZZero,         // is XYZ zero
+    output logic                    XZero, YZero, ZZero, // is XYZ zero
-    output logic                    XInf, YInf, ZInf,            // is XYZ infinity
+    output logic                    XInf, YInf, ZInf,    // is XYZ infinity
-    output logic                    XExpMax                        // does X have the maximum exponent (NaN or Inf)
+    output logic                    XExpMax              // does X have the maximum exponent (NaN or Inf)
 );
  
-    logic           XExpNonZero, YExpNonZero, ZExpNonZero; // is the exponent of XYZ non-zero
+    logic XExpNonZero, YExpNonZero, ZExpNonZero; // is the exponent of XYZ non-zero
-    logic           XFracZero, YFracZero, ZFracZero; // is the fraction zero
+    logic XFracZero, YFracZero, ZFracZero;      // is the fraction zero
-    logic           YExpMax, ZExpMax;  // is the exponent all 1s
+    logic YExpMax, ZExpMax;                     // is the exponent all 1s
     
     unpackinput unpackinputX (.In(X), .Fmt, .Sgn(Xs), .Exp(Xe), .Man(Xm), .En(XEn),
                             .NaN(XNaN), .SNaN(XSNaN), .ExpNonZero(XExpNonZero),
@@ -59,6 +57,6 @@ module unpack (
     unpackinput unpackinputZ (.In(Z), .Fmt, .Sgn(Zs), .Exp(Ze), .Man(Zm), .En(ZEn),
                             .NaN(ZNaN), .SNaN(ZSNaN), .ExpNonZero(ZExpNonZero),
                             .Zero(ZZero), .Inf(ZInf), .ExpMax(ZExpMax), .FracZero(ZFracZero));
-    // is the input Subnormalized
+    // is the input subnormal
     assign XSubnorm = ~XExpNonZero & ~XFracZero;
  endmodule

pipelined/src/fpu/unpackinput.sv

@@ -4,57 +4,56 @@
 // Written: me@KatherineParry.com
 // Modified: 7/5/2022
 //
-// Purpose: unpack input
+// Purpose: unpack input: extract sign, exponent, significand, characteristics
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 13
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 `include "wally-config.vh"
 
 module unpackinput ( 
-    input logic  [`FLEN-1:0]        In,    // inputs from register file
+    input  logic [`FLEN-1:0]        In,         // inputs from register file
-    input logic                     En,     // enable the input
+    input  logic                    En,         // enable the input
-    input logic  [`FMTBITS-1:0]     Fmt,       // format signal 00 - single 01 - double 11 - quad 10 - half
+    input  logic [`FMTBITS-1:0]     Fmt,        // format signal 00 - single 01 - double 11 - quad 10 - half
-    output logic                    Sgn,    // sign bits of XYZ
+    output logic                    Sgn,        // sign bits of XYZ
-    output logic [`NE-1:0]          Exp,    // exponents of XYZ (converted to largest supported precision)
+    output logic [`NE-1:0]          Exp,        // exponents of XYZ (converted to largest supported precision)
-    output logic [`NF:0]            Man,    // mantissas of XYZ (converted to largest supported precision)
+    output logic [`NF:0]            Man,        // mantissas of XYZ (converted to largest supported precision)
-    output logic                    NaN,    // is XYZ a NaN
+    output logic                    NaN,        // is XYZ a NaN
-    output logic                    SNaN, // is XYZ a signaling NaN
+    output logic                    SNaN,       // is XYZ a signaling NaN
-    output logic                    Zero,         // is XYZ zero
+    output logic                    Zero,       // is XYZ zero
-    output logic                    Inf,            // is XYZ infinity
+    output logic                    Inf,        // is XYZ infinity
-    output logic                    ExpNonZero,            // is the exponent not zero
+    output logic                    ExpNonZero, // is the exponent not zero
-    output logic                    FracZero,            // is the fraction zero
+    output logic                    FracZero,   // is the fraction zero
-    output logic                    ExpMax                       // does In have the maximum exponent (NaN or Inf)
+    output logic                    ExpMax      // does In have the maximum exponent (NaN or Inf)
 );
  
-    logic [`NF-1:0] Frac; //Fraction of XYZ
+    logic [`NF-1:0] Frac;       // Fraction of XYZ
-    logic           BadNaNBox;
+    logic           BadNaNBox;  // is the NaN boxing bad
     
     if (`FPSIZES == 1) begin        // if there is only one floating point format supported
         assign BadNaNBox = 0;
         assign Sgn = In[`FLEN-1];  // sign bit
         assign Frac = In[`NF-1:0];  // fraction (no assumed 1)
         assign ExpNonZero = |In[`FLEN-2:`NF];  // is the exponent non-zero
-        assign Exp = {In[`FLEN-2:`NF+1], In[`NF]|~ExpNonZero};  // exponent.  Subnormalized numbers have effective biased exponent of 1
+        assign Exp = {In[`FLEN-2:`NF+1], In[`NF]|~ExpNonZero};  // exponent.  subnormal numbers have effective biased exponent of 1
         assign ExpMax = &In[`FLEN-2:`NF];  // is the exponent all 1's
+    
     end else if (`FPSIZES == 2) begin   // if there are 2 floating point formats supported
         //***need better names for these constants
         // largest format | smaller format

pipelined/src/generic/adder.sv

@@ -6,26 +6,22 @@
 //
 // Purpose: Adder
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/generic/aplusbeq0.sv

@@ -6,26 +6,22 @@
 //
 // Purpose: Determine if A+B = 0.  Used in FP divider.
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/generic/arrs.sv

@@ -9,26 +9,22 @@
 //          arrs takes in the asynchronous reset and outputs an asynchronous
 //          rising edge, but then syncs the falling edge to the posedge clk.
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/generic/binencoder.sv

@@ -5,7 +5,7 @@
 //
 // Purpose: one-hot to binary encoding.
 //
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 //
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/clockgater.sv

@@ -6,26 +6,22 @@
 //
 // Purpose: Clock gater model. Must use standard cell for synthesis.
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/generic/counter.sv

@@ -6,26 +6,22 @@
 //
 // Purpose: Counter with reset and enable
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/generic/csa.sv

@@ -6,26 +6,22 @@
 //
 // Purpose: 3:2 carry-save adder
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module csa #(parameter N=16) (

pipelined/src/generic/decoder.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Binary encoding to one-hot decoder
 //
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 //
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/flop/flop.sv

@@ -4,33 +4,28 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: various flavors of flip-flops
+// Purpose: D flip-flop
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
 
-// ordinary flip-flop
 module flop #(parameter WIDTH = 8) ( 
   input  logic             clk,
   input  logic [WIDTH-1:0] d, 

pipelined/src/generic/flop/flopen.sv

@@ -4,33 +4,28 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: various flavors of flip-flops
+// Purpose: D flip-flop with enable
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
 
-// flop with enable
 module flopen #(parameter WIDTH = 8) (
   input  logic             clk, en,
   input  logic [WIDTH-1:0] d, 

pipelined/src/generic/flop/flopenl.sv

@@ -4,33 +4,28 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: various flavors of flip-flops
+// Purpose: D flip-flop with enable and synchronous load
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
 
-// flop with enable, synchronous load
 module flopenl #(parameter WIDTH = 8, parameter type TYPE=logic [WIDTH-1:0]) (
   input  logic clk, load, en,
   input  TYPE d,

pipelined/src/generic/flop/flopenr.sv

@@ -4,33 +4,28 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: various flavors of flip-flops
+// Purpose: D flip-flop with enable, synchronous reset
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
 
-// flop with enable, synchronous reset
 module flopenr #(parameter WIDTH = 8) (
   input  logic             clk, reset, en,
   input  logic [WIDTH-1:0] d, 

pipelined/src/generic/flop/flopenrc.sv

@@ -4,33 +4,28 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: various flavors of flip-flops
+// Purpose: D flip-flop with enable, synchronous reset, enabled clear
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
 
-// flop with enable, synchronous reset, enabled clear
 module flopenrc #(parameter WIDTH = 8) (
   input  logic             clk, reset, clear, en,
   input  logic [WIDTH-1:0] d, 

pipelined/src/generic/flop/flopens.sv

@@ -4,33 +4,28 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: various flavors of flip-flops
+// Purpose: D flip-flop with enable, synchronous set
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
 
-// flop with enable, synchronous set
 module flopens #(parameter WIDTH = 8) (
   input  logic             clk, set, en,
   input  logic [WIDTH-1:0] d, 

pipelined/src/generic/flop/flopr.sv

@@ -4,33 +4,28 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: various flavors of flip-flops
+// Purpose: D flip-flop with synchronous reset
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
 
-// flop with synchronous reset
 module flopr #(parameter WIDTH = 8) ( 
   input  logic             clk, reset,
   input  logic [WIDTH-1:0] d, 

pipelined/src/generic/flop/floprc.sv

@@ -4,33 +4,28 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: various flavors of flip-flops
+// Purpose: D flip-flop with synchronous reset and clear
 //
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
 
-// flop with synchronous reset, synchronous clear
 module floprc #(parameter WIDTH = 8) (
   input  logic clk,
   input  logic reset,

pipelined/src/generic/flop/synchronizer.sv

@@ -6,31 +6,26 @@
 //
 // Purpose: Two-stage flip-flop synchronizer
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
 
-// ordinary flip-flop
 module synchronizer ( 
   input  logic clk,
   input  logic d, 

pipelined/src/generic/lzc.sv

@@ -5,31 +5,28 @@
 //
 // Purpose: Leading Zero Counter
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
+
 //leading zero counter i.e. priority encoder
 module lzc #(parameter WIDTH = 1) (
-    input logic  [WIDTH-1:0]            num,
+    input logic  [WIDTH-1:0]            num,    // number to count the leading zeroes of
-    output logic [$clog2(WIDTH+1)-1:0]  ZeroCnt
+    output logic [$clog2(WIDTH+1)-1:0]  ZeroCnt // the number of leading zeroes
 );
 /* verilator lint_off CMPCONST */
 /* verilator lint_off WIDTH */

pipelined/src/generic/mem/ram1p1rwbe.sv

@@ -9,26 +9,22 @@
 //
 // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 // WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words

pipelined/src/generic/mem/ram2p1r1wb.sv

@@ -16,26 +16,22 @@
 // example
 // mem load -infile twoBitPredictor.txt -format bin testbench/dut/core/ifu/bpred/DirPredictor/memory/memory
 //
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/generic/mem/ram2p1rwbefix.sv

@@ -9,26 +9,22 @@
 //
 // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 // WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words

pipelined/src/generic/mem/rom1p1r.sv

@@ -5,26 +5,22 @@
 //
 // Purpose: Single-ported ROM
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 // This model actually works correctly with vivado.

pipelined/src/generic/mux.sv

@@ -6,26 +6,22 @@
 //
 // Purpose: Various flavors of multiplexers
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/generic/neg.sv

@@ -6,26 +6,22 @@
 //
 // Purpose: 2's complement negator
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/generic/onehotdecoder.sv

@@ -6,26 +6,22 @@
 //
 // Purpose: Bin to one hot decoder. Power of 2 only.
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/generic/or_rows.sv

@@ -6,26 +6,22 @@
 //
 // Purpose: Various flavors of multiplexers
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/generic/priorityonehot.sv

@@ -16,7 +16,7 @@
 //        in  01011101010100000
 //        out 00000000000100000
 //
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 //
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/generic/prioritythermometer.sv

@@ -12,7 +12,7 @@
 //        in  01011101010100000
 //        out 00000000000011111
 //
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 //
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
 //

pipelined/src/hazard/hazard.sv

@@ -6,26 +6,22 @@
 //
 // Purpose: Determine forwarding, stalls and flushes
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/ieu/alu.sv

@@ -1,31 +1,30 @@
 ///////////////////////////////////////////
 // alu.sv
 //
-// Written: David_Harris@hmc.edu 9 January 2021
+// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu
+// Created: 9 January 2021
 // Modified: 
 //
 // Purpose: RISC-V Arithmetic/Logic Unit
 //
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4)
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/ieu/comparator.sv

@@ -6,26 +6,24 @@
 //
 // Purpose: Branch comparison
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.7)
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/ieu/controller.sv

@@ -6,26 +6,24 @@
 //
 // Purpose: Top level controller module
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.1.4, Figure 4.8, Table 4.5)
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
@@ -49,7 +47,7 @@ module controller(
   output logic       ALUResultSrcE,
   output logic       MemReadE, CSRReadE, // for Hazard Unit
   output logic [2:0] Funct3E,
-  output logic       MDUE, W64E,
+  output logic       IntDivE, MDUE, W64E,
   output logic       JumpE,	
   output logic       SCE,
   output logic       BranchSignedE,
@@ -65,7 +63,7 @@ module controller(
   output logic       FWriteIntM,
   // Writeback stage control signals
   input  logic       StallW, FlushW,
-  output logic 	     RegWriteW, DivW,    // for datapath and Hazard Unit
+  output logic 	     RegWriteW, IntDivW,    // for datapath and Hazard Unit
   output logic [2:0] ResultSrcW,
   // Stall during CSRs
   //output logic       CSRWriteFencePendingDEM,
@@ -111,7 +109,7 @@ module controller(
   logic [1:0]  AtomicE;
    logic       FenceD, FenceE, FenceM;
   logic        SFenceVmaD;
-   logic       DivE, DivM;
+   logic       IntDivM;
    
 
   // Extract fields
@@ -231,17 +229,17 @@ module controller(
   assign MemReadE = MemRWE[1];
   assign SCE = (ResultSrcE == 3'b100);
   assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers
-  assign DivE = MDUE & Funct3E[2]; // Division operation
+  assign IntDivE = MDUE & Funct3E[2]; // Integer division operation
   
   // Memory stage pipeline control register
   flopenrc #(20) controlregM(clk, reset, FlushM, ~StallM,
-                         {RegWriteE, ResultSrcE, MemRWE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, FWriteIntE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE, DivE},
+                         {RegWriteE, ResultSrcE, MemRWE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, FWriteIntE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE, IntDivE},
-                         {RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, FWriteIntM, AtomicM, InvalidateICacheM, FlushDCacheM, FenceM, InstrValidM, DivM});
+                         {RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, FWriteIntM, AtomicM, InvalidateICacheM, FlushDCacheM, FenceM, InstrValidM, IntDivM});
   
   // Writeback stage pipeline control register
   flopenrc #(5) controlregW(clk, reset, FlushW, ~StallW,
-                         {RegWriteM, ResultSrcM, DivM},
+                         {RegWriteM, ResultSrcM, IntDivM},
-                         {RegWriteW, ResultSrcW, DivW});  
+                         {RegWriteW, ResultSrcW, IntDivW});  
 
   // Flush F, D, and E stages on a CSR write or Fence.I or SFence.VMA
   assign CSRWriteFenceM = CSRWriteM | FenceM;

pipelined/src/ieu/datapath.sv

@@ -1,31 +1,29 @@
 ///////////////////////////////////////////
 // datapath.sv
 //
-// Written: David_Harris@hmc.edu 9 January 2021
+// Written: sarahleilani@gmail.com and David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
 // Purpose: Wally Integer Datapath
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12)
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
@@ -57,13 +55,13 @@ module datapath (
   output logic [`XLEN-1:0] WriteDataM, 
   // Writeback stage signals
   input  logic             StallW, FlushW,
-(* mark_debug = "true" *)  input  logic             RegWriteW, DivW,
+(* mark_debug = "true" *)  input  logic             RegWriteW, IntDivW,
   input  logic             SquashSCW,
   input  logic [2:0]       ResultSrcW,
   input logic [`XLEN-1:0]  FCvtIntResW,
   input logic [`XLEN-1:0] ReadDataW,
   input  logic [`XLEN-1:0] CSRReadValW, MDUResultW, 
-  input logic [`XLEN-1:0] FPIntDivResultW,
+  input logic [`XLEN-1:0] FIntDivResultW,
    // Hazard Unit signals 
   output logic [4:0]       Rs1D, Rs2D, Rs1E, Rs2E,
   output logic [4:0]       RdE, RdM, RdW 
@@ -126,7 +124,7 @@ module datapath (
     mux2  #(`XLEN)  resultmuxM(IEUResultM, FIntResM, FWriteIntM, IFResultM);
     mux2  #(`XLEN)  cvtresultmuxW(IFResultW, FCvtIntResW, FCvtIntW, IFCvtResultW);
     if (`IDIV_ON_FPU) begin
-      mux2  #(`XLEN)  divresultmuxW(MDUResultW, FPIntDivResultW, DivW, MulDivResultW);
+      mux2  #(`XLEN)  divresultmuxW(MDUResultW, FIntDivResultW, IntDivW, MulDivResultW);
     end else begin 
       assign MulDivResultW = MDUResultW;
     end

pipelined/src/ieu/extend.sv

@@ -4,28 +4,26 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: 
+// Purpose: Produce sign-extended immediates from various formats
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.3)
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/ieu/forward.sv

@@ -6,26 +6,24 @@
 //
 // Purpose: Determine datapath forwarding
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.2.2.3)
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/ieu/ieu.sv

@@ -6,26 +6,24 @@
 //
 // Purpose: Integer Execution Unit: datapath and controller
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12)
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
@@ -41,7 +39,7 @@ module ieu (
   input logic [`XLEN-1:0]  PCLinkE,
   input logic 		   FWriteIntE, FCvtIntE, FCvtIntW,
   output logic [`XLEN-1:0] IEUAdrE,
-  output logic 		   MDUE, W64E,
+  output logic 		   IntDivE, W64E,
   output logic [2:0] 	   Funct3E,
   output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // these are the src outputs before the mux choosing between them and PCE to put in srcA/B
 
@@ -58,7 +56,7 @@ module ieu (
   output logic       InvalidateICacheM, FlushDCacheM,
 
   // Writeback stage
-  input logic [`XLEN-1:0] FPIntDivResultW,
+  input logic [`XLEN-1:0] FIntDivResultW,
   input logic [`XLEN-1:0]  CSRReadValW, MDUResultW,
   input logic [`XLEN-1:0]  FCvtIntResW,
   output logic [4:0]       RdW,
@@ -82,7 +80,7 @@ module ieu (
   logic        ALUResultSrcE;
   logic        SCE;
   logic        FWriteIntM;
-  logic        DivW;
+  logic        IntDivW;
 
   // forwarding signals
   logic [4:0]       Rs1D, Rs2D, Rs1E, Rs2E;
@@ -91,23 +89,24 @@ module ieu (
   logic             MemReadE, CSRReadE;
   logic             JumpE;
   logic             BranchSignedE;
+  logic             MDUE;
            
   controller c(
     .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD,
     .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, .StallE, .FlushE, .FlagsE, .FWriteIntE,
     .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .MemReadE, .CSRReadE, 
-    .Funct3E, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM,
+    .Funct3E, .IntDivE, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM,
     .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M,
     .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .FWriteIntM,
-    .StallW, .FlushW, .RegWriteW, .DivW, .ResultSrcW, .CSRWriteFenceM, .StoreStallD);
+    .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .StoreStallD);
 
   datapath   dp(
     .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE,
     .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .BranchSignedE, 
     .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, 
     .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW,
-    .StallW, .FlushW, .RegWriteW, .DivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW,
+    .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW,
-    .CSRReadValW, .MDUResultW, .FPIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW);             
+    .CSRReadValW, .MDUResultW, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW);             
   
   forward    fw(
     .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW,

pipelined/src/ieu/regfile.sv

@@ -6,26 +6,24 @@
 //
 // Purpose: 3-port register file
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 4
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/ieu/shifter.sv

@@ -6,26 +6,24 @@
 //
 // Purpose: RISC-V 32/64 bit shifter
 // 
-// A component of the Wally configurable RISC-V project.
+// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.5, Table 4.3)
 //
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// MIT LICENSE
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//   substantial portions of the Software.
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// may obtain a copy of the License at
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// https://solderpad.org/licenses/SHL-2.1/
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/ifu/BTBPredictor.sv

@@ -9,26 +9,22 @@
 // Purpose: BTB model.  Outputs type of instruction (currently 1 hot encoded. Probably want 
 // to encode to reduce storage), valid, target PC.
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/ifu/RAsPredictor.sv

@@ -8,26 +8,22 @@
 //
 // Purpose: 2 bit saturating counter predictor with parameterized table depth.
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"

pipelined/src/ifu/bpred.sv

@@ -9,26 +9,22 @@
 // Purpose: Branch prediction unit
 //          Produces a branch prediction based on branch history.
 // 
-// A component of the Wally configurable RISC-V project.
+// A component of the CORE-V-WALLY configurable RISC-V project.
 // 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
 //
-// MIT LICENSE
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
-// software and associated documentation files (the "Software"), to deal in the Software 
-// without restriction, including without limitation the rights to use, copy, modify, merge, 
-// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
-// to whom the Software is furnished to do so, subject to the following conditions:
 //
-//   The above copyright notice and this permission notice shall be included in all copies or 
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-//   substantial portions of the Software.
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
 //
-//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+// https://solderpad.org/licenses/SHL-2.1/
-//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//
-//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
-//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+// either express or implied. See the License for the specific language governing permissions 
-//   OR OTHER DEALINGS IN THE SOFTWARE.
+// and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
@@ -107,29 +103,12 @@ module bpred (
       .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
       .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
 
-  end else if (`BPTYPE == "BPFOLDEDGSHARE") begin:Predictor
-    foldedgshare #(16, 10) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
-      .BranchInstrF(BPInstrClassF[0]), .BranchInstrD(BPInstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),
-      .BranchInstrW(InstrClassW[0]), .PCSrcE);
-	
   end else if (`BPTYPE == "BPSPECULATIVEGSHARE") begin:Predictor
     speculativegshare DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
       .BranchInstrF(BPInstrClassF[0]), .BranchInstrD(BPInstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),
       .BranchInstrW(InstrClassW[0]), .PCSrcE);
 
-  end else if (`BPTYPE == "BPOLDGSHARE") begin:Predictor
-    oldgsharepredictor DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
-      .BPInstrClassF, .BPInstrClassD, .BPInstrClassE,
-      .InstrClassE, .PCSrcE);
-
-  end else if (`BPTYPE == "BPOLDGSHARE2") begin:Predictor
-    oldgsharepredictor2 DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-      .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
-      .BPInstrClassF, .BPInstrClassD, .BPInstrClassE,
-      .InstrClassE, .PCSrcE);
   end else if (`BPTYPE == "BPLOCALPAg") begin:Predictor
     // *** Fix me
 /* -----\/----- EXCLUDED -----\/-----