forked from Github_Repos/cvw
38 lines
1.3 KiB
Systemverilog
38 lines
1.3 KiB
Systemverilog
///////////////////////////////////////////
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// fmamult.sv
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//
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// Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu
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// Modified:
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//
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// Purpose: FMA Significand Multiplier
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//
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// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.7)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module fmamult(
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input logic [`NF:0] Xm, Ym, // x and y significand
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output logic [2*`NF+1:0] Pm // product's significand
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);
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assign Pm = Xm * Ym;
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endmodule
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