forked from Github_Repos/cvw
72 lines
2.7 KiB
Systemverilog
72 lines
2.7 KiB
Systemverilog
///////////////////////////////////////////
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// 1 port sram.
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//
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// Written: ross1728@gmail.com May 3, 2021
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// Basic sram with 1 read write port.
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// When clk rises Addr and LineWriteData are sampled.
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// Following the clk edge read data is output from the sampled Addr.
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// Write
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//
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// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
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`include "wally-config.vh"
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module ram2p1r1wbefix #(parameter DEPTH=128, WIDTH=256) (
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input logic clk,
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input logic ce1, ce2,
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input logic [$clog2(DEPTH)-1:0] ra1,
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input logic [WIDTH-1:0] wd2,
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input logic [$clog2(DEPTH)-1:0] wa2,
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input logic we2,
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input logic [(WIDTH-1)/8:0] bwe2,
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output logic [WIDTH-1:0] rd1);
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logic [WIDTH-1:0] mem[DEPTH-1:0];
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// ***************************************************************************
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// TRUE Smem macro
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// ***************************************************************************
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// ***************************************************************************
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// READ first SRAM model
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// ***************************************************************************
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integer i;
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// Read
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always @(posedge clk)
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if(ce1) rd1 <= #1 mem[ra1];
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// Write divided into part for bytes and part for extra msbs
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if(WIDTH >= 8)
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always @(posedge clk)
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if (ce2 & we2)
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for(i = 0; i < WIDTH/8; i++)
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if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8];
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if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
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always @(posedge clk)
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if (ce2 & we2 & bwe2[WIDTH/8])
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mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8];
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endmodule
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