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Square root negative exponent handling
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@ -1,6 +1,6 @@
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/* sqrttestgen.c */
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/* sqrttestgen.c */
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/* Written 19 October 2021 David_Harris@hmc.edu
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/* Written 7/22/2022 by Cedar Turek
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This program creates test vectors for mantissa component
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This program creates test vectors for mantissa component
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of an IEEE floating point square root.
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of an IEEE floating point square root.
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@ -15,6 +15,7 @@
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/* Constants */
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/* Constants */
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#define ENTRIES 17
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#define ENTRIES 17
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#define BIGENT 1000
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#define RANDOM_VECS 500
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#define RANDOM_VECS 500
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/* Prototypes */
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/* Prototypes */
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@ -34,6 +35,9 @@ void main(void)
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1.75, 1.875, 1.99999,
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1.75, 1.875, 1.99999,
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1.1, 1.5, 1.01, 1.001, 1.0001,
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1.1, 1.5, 1.01, 1.001, 1.0001,
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2/1.1, 2/1.5, 2/1.25, 2/1.125};
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2/1.1, 2/1.5, 2/1.25, 2/1.125};
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double bigtest[BIGENT];
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double exps[ENTRIES] = {0, 0, 2, 3, 4, 5, 6, 7, 8, 1, 10,
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double exps[ENTRIES] = {0, 0, 2, 3, 4, 5, 6, 7, 8, 1, 10,
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11, 12, 13, 14, 15, 16};
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11, 12, 13, 14, 15, 16};
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int i;
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int i;
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@ -44,13 +48,14 @@ void main(void)
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exit(1);
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exit(1);
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}
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}
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for (i=0; i<ENTRIES; i++) {
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// Small Test
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aFrac = mans[i];
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// for (i=0; i<ENTRIES; i++) {
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aExp = exps[i] + bias;
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// aFrac = mans[i];
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rFrac = sqrt(aFrac * pow(2, exps[i]));
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// aExp = exps[i] + bias;
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rExp = (int) (log(rFrac)/log(2) + bias);
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// rFrac = sqrt(aFrac * pow(2, exps[i]));
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output(fptr, aExp, aFrac, rExp, rFrac);
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// rExp = (int) (log(rFrac)/log(2) + bias);
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}
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// output(fptr, aExp, aFrac, rExp, rFrac);
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// }
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// WS
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// WS
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// Test 1: sqrt(1) = 1 0000 0000 0000 00
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// Test 1: sqrt(1) = 1 0000 0000 0000 00
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@ -67,6 +72,16 @@ void main(void)
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// output(fptr, a, r);
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// output(fptr, a, r);
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// }
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// }
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// Big Test
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for (i=0; i<BIGENT; i++) {
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bigtest[i] = random_input();
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aFrac = bigtest[i];
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aExp = (i - BIGENT/2) + bias;
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rFrac = sqrt(aFrac * pow(2, (i - BIGENT/2)));
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rExp = (int) (log(rFrac)/log(2) + bias);
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output(fptr, aExp, aFrac, rExp, rFrac);
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}
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fclose(fptr);
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fclose(fptr);
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}
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}
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@ -105,6 +120,6 @@ void printhex(FILE *fptr, double m)
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double random_input(void)
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double random_input(void)
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{
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{
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return 1.0 + rand()/32767.0;
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return 1.0 + ((rand() % 32768)/32767.0);
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}
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}
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@ -3,4 +3,5 @@ add wave -noupdate /testbench/srt/*
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add wave -noupdate /testbench/srt/sotfc2/*
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add wave -noupdate /testbench/srt/sotfc2/*
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add wave -noupdate /testbench/srt/preproc/*
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add wave -noupdate /testbench/srt/preproc/*
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add wave -noupdate /testbench/srt/postproc/*
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add wave -noupdate /testbench/srt/postproc/*
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add wave -noupdate /testbench/srt/expcalc/*
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add wave -noupdate /testbench/srt/divcounter/*
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add wave -noupdate /testbench/srt/divcounter/*
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@ -389,11 +389,11 @@ module expcalc(
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input logic Sqrt,
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input logic Sqrt,
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output logic [`NE-1:0] calcExp
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output logic [`NE-1:0] calcExp
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);
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);
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logic [`NE-1:0] SExp, DExp, SXExp;
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logic [`NE+1:0] SExp, DExp, SXExp;
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assign SXExp = XExp - (`NE)'(`BIAS);
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assign SXExp = {2'b00, XExp} - (`NE+2)'(`BIAS);
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assign SExp = {1'b0, SXExp[`NE-1:1]} + (`NE)'(`BIAS);
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assign SExp = (SXExp >> 1) + (`NE+2)'(`BIAS);
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assign DExp = XExp - YExp + (`NE)'(`BIAS);
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assign DExp = {2'b00, XExp} - {2'b00, YExp} + (`NE+2)'(`BIAS);
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assign calcExp = Sqrt ? SExp : DExp;
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assign calcExp = Sqrt ? SExp[`NE-1:0] : DExp[`NE-1:0];
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endmodule
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endmodule
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@ -462,11 +462,13 @@ module srtpostproc(
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end
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end
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assign floatRes = S[`DIVLEN] ? S[`DIVLEN:1] : S[`DIVLEN-1:0];
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assign floatRes = S[`DIVLEN] ? S[`DIVLEN:1] : S[`DIVLEN-1:0];
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assign intRes = intS[`DIVLEN] ? intS[`DIVLEN:1] : intS[`DIVLEN-1:0];
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assign intRes = intS[`DIVLEN] ? intS[`DIVLEN:1] : intS[`DIVLEN-1:0];
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assign shiftRem = (intRem >>> (`DIVLEN - dur + 2));
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assign shiftRem = (intRem >> (zeroCntD));
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always_comb
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always_comb begin
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if (Int) Result = intRes >> (`DIVLEN - dur);
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if (Int) begin
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else if (Mod) Result = shiftRem[`DIVLEN-1:0];
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if (Mod) Result = shiftRem[`DIVLEN-1:0];
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else Result = floatRes;
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else Result = intRes >> (`DIVLEN - dur);
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end else Result = floatRes;
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end
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assign calcSign = XSign ^ YSign;
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assign calcSign = XSign ^ YSign;
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endmodule
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endmodule
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@ -53,7 +53,7 @@ module testbench;
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// Test parameters
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// Test parameters
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parameter MEM_SIZE = 40000;
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parameter MEM_SIZE = 40000;
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parameter MEM_WIDTH = 64+64+64+64;
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parameter MEM_WIDTH = 64+64+64;
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// Test sizes
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// Test sizes
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`define memr 63:0
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`define memr 63:0
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@ -70,9 +70,9 @@ module testbench;
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integer testnum, errors;
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integer testnum, errors;
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// Equip Int, Sqrt, or IntMod test
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// Equip Int, Sqrt, or IntMod test
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assign Int = 1'b1;
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assign Int = 1'b0;
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assign Mod = 1'b0;
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assign Mod = 1'b0;
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assign Sqrt = 1'b0;
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assign Sqrt = 1'b1;
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// Divider
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// Divider
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srt srt(.clk, .Start(req),
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srt srt(.clk, .Start(req),
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begin
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begin
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testnum = 0;
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testnum = 0;
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errors = 0;
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errors = 0;
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$readmemh ("inttestvectors", Tests);
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$readmemh ("sqrttestvectors", Tests);
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Vec = Tests[testnum];
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Vec = Tests[testnum];
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a = Vec[`mema];
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a = Vec[`mema];
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{asign, aExp, afrac} = a;
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{asign, aExp, afrac} = a;
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