diff --git a/pipelined/srt/sqrttestgen b/pipelined/srt/sqrttestgen index 45fc6e78..7c6efb9f 100755 Binary files a/pipelined/srt/sqrttestgen and b/pipelined/srt/sqrttestgen differ diff --git a/pipelined/srt/sqrttestgen.c b/pipelined/srt/sqrttestgen.c index 7a45449f..17edc528 100644 --- a/pipelined/srt/sqrttestgen.c +++ b/pipelined/srt/sqrttestgen.c @@ -1,6 +1,6 @@ /* sqrttestgen.c */ -/* Written 19 October 2021 David_Harris@hmc.edu +/* Written 7/22/2022 by Cedar Turek This program creates test vectors for mantissa component of an IEEE floating point square root. @@ -15,6 +15,7 @@ /* Constants */ #define ENTRIES 17 +#define BIGENT 1000 #define RANDOM_VECS 500 /* Prototypes */ @@ -34,6 +35,9 @@ void main(void) 1.75, 1.875, 1.99999, 1.1, 1.5, 1.01, 1.001, 1.0001, 2/1.1, 2/1.5, 2/1.25, 2/1.125}; + + double bigtest[BIGENT]; + double exps[ENTRIES] = {0, 0, 2, 3, 4, 5, 6, 7, 8, 1, 10, 11, 12, 13, 14, 15, 16}; int i; @@ -44,13 +48,14 @@ void main(void) exit(1); } - for (i=0; i> 1) + (`NE+2)'(`BIAS); + assign DExp = {2'b00, XExp} - {2'b00, YExp} + (`NE+2)'(`BIAS); + assign calcExp = Sqrt ? SExp[`NE-1:0] : DExp[`NE-1:0]; endmodule @@ -462,11 +462,13 @@ module srtpostproc( end assign floatRes = S[`DIVLEN] ? S[`DIVLEN:1] : S[`DIVLEN-1:0]; assign intRes = intS[`DIVLEN] ? intS[`DIVLEN:1] : intS[`DIVLEN-1:0]; - assign shiftRem = (intRem >>> (`DIVLEN - dur + 2)); - always_comb - if (Int) Result = intRes >> (`DIVLEN - dur); - else if (Mod) Result = shiftRem[`DIVLEN-1:0]; - else Result = floatRes; + assign shiftRem = (intRem >> (zeroCntD)); + always_comb begin + if (Int) begin + if (Mod) Result = shiftRem[`DIVLEN-1:0]; + else Result = intRes >> (`DIVLEN - dur); + end else Result = floatRes; + end assign calcSign = XSign ^ YSign; endmodule diff --git a/pipelined/srt/testbench.sv b/pipelined/srt/testbench.sv index 513305b2..1b40c673 100644 --- a/pipelined/srt/testbench.sv +++ b/pipelined/srt/testbench.sv @@ -53,7 +53,7 @@ module testbench; // Test parameters parameter MEM_SIZE = 40000; - parameter MEM_WIDTH = 64+64+64+64; + parameter MEM_WIDTH = 64+64+64; // Test sizes `define memr 63:0 @@ -70,9 +70,9 @@ module testbench; integer testnum, errors; // Equip Int, Sqrt, or IntMod test - assign Int = 1'b1; + assign Int = 1'b0; assign Mod = 1'b0; - assign Sqrt = 1'b0; + assign Sqrt = 1'b1; // Divider srt srt(.clk, .Start(req), @@ -101,7 +101,7 @@ module testbench; begin testnum = 0; errors = 0; - $readmemh ("inttestvectors", Tests); + $readmemh ("sqrttestvectors", Tests); Vec = Tests[testnum]; a = Vec[`mema]; {asign, aExp, afrac} = a;