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cvw/wally-pipelined/regression/wave.do

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Cleanup of the branch predictor flush and stall controls.
2021-03-12 20:57:53 +00:00
onerror {resume}
Wrote a bash script to generate custom modelsim radix which maps instruction addresses into human readable lables. Once combined with some simulation verilog this will display the current function in modelsim.
2021-02-18 04:20:28 +00:00
quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/clk
add wave -noupdate /testbench/reset
Finally I think I have the function radix mapping across all applications correctly. I still need to clean up the code a bit so it is easier to understand.
2021-03-10 17:00:51 +00:00
add wave -noupdate /testbench/test
minor change to wave file.
2021-02-19 15:08:13 +00:00
add wave -noupdate -radix ascii /testbench/memfilename
Cleanup of the branch predictor flush and stall controls.
2021-03-12 20:57:53 +00:00
add wave -noupdate -expand -group {Execution Stage} /testbench/functionRadix/function_radix/FunctionName
Added FlushF to hazard unit. Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined. I will look this up and add it to the compiler.
2021-02-19 22:36:51 +00:00
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
Fixed a bunch of bugs with the RAS.
2021-03-24 02:49:16 +00:00
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/RetM
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/TrapM
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/InstrStall
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/DataStall
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/ifu/StallE
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/ifu/StallM
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/ifu/StallW
fixed issue with BTB's valid bit not updating. There is still a problem is valid not ocurring in the correct clock cycle.
2021-03-24 01:06:45 +00:00
add wave -noupdate -expand -group Bpred -expand -group direction -color Yellow /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/GHRF
add wave -noupdate -expand -group Bpred -expand -group direction -divider Lookup
add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/LookUpPC
add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/LookUpPCIndex
add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/PredictionMemory
add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/Prediction
add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/BPPredF
add wave -noupdate -expand -group Bpred -expand -group direction -expand -group output /testbench/dut/hart/ifu/bpred/BPPredPCF
add wave -noupdate -expand -group Bpred -expand -group direction -expand -group output /testbench/dut/hart/ifu/bpred/SelBPPredF
add wave -noupdate -expand -group Bpred -expand -group direction -divider Update
add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/UpdatePC
add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/UpdatePCIndex
add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/UpdateEN
add wave -noupdate -expand -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/UpdatePrediction
add wave -noupdate -expand -group Bpred -expand -group direction -group other /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/DoForwarding
add wave -noupdate -expand -group Bpred -expand -group direction -group other /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/DoForwardingF
add wave -noupdate -expand -group Bpred -expand -group direction -group other /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/GHRD
add wave -noupdate -expand -group Bpred -expand -group direction -group other /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/GHRE
Fixed a bunch of bugs with the RAS.
2021-03-24 02:49:16 +00:00
add wave -noupdate -expand -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/TargetWrongE
add wave -noupdate -expand -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/FallThroughWrongE
add wave -noupdate -expand -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/PredictionDirWrongE
add wave -noupdate -expand -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/PredictionPCWrongE
add wave -noupdate -expand -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/BPPredWrongE
add wave -noupdate -expand -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/InstrClassE
add wave -noupdate -expand -group Bpred -group {bp wrong} -divider pcs
add wave -noupdate -expand -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/PCD
add wave -noupdate -expand -group Bpred -group {bp wrong} /testbench/dut/hart/ifu/bpred/PCTargetE
fixed a whole bunch of bugs with the branch predictor. Still an issue with how PCNextF is not updated because the CPU is stalled.
2021-03-23 21:53:48 +00:00
add wave -noupdate -expand -group Bpred -expand -group BTB -divider Update
add wave -noupdate -expand -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdateEN
add wave -noupdate -expand -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdatePC
add wave -noupdate -expand -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/InstrClassE
add wave -noupdate -expand -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdateTarget
fixed issue with BTB's valid bit not updating. There is still a problem is valid not ocurring in the correct clock cycle.
2021-03-24 01:06:45 +00:00
add wave -noupdate -expand -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdatePCIndexQ
fixed a whole bunch of bugs with the branch predictor. Still an issue with how PCNextF is not updated because the CPU is stalled.
2021-03-23 21:53:48 +00:00
add wave -noupdate -expand -group Bpred -expand -group BTB -divider Lookup
add wave -noupdate -expand -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/TargetPC
add wave -noupdate -expand -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/InstrClass
add wave -noupdate -expand -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/Valid
add wave -noupdate -expand -group Bpred /testbench/dut/hart/ifu/bpred/BPPredWrongE
Fixed a bunch of bugs with the RAS.
2021-03-24 02:49:16 +00:00
add wave -noupdate -expand -group Bpred -expand -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/pop
add wave -noupdate -expand -group Bpred -expand -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/push
add wave -noupdate -expand -group Bpred -expand -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/pushPC
add wave -noupdate -expand -group Bpred -expand -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/PtrD
add wave -noupdate -expand -group Bpred -expand -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/PtrQ
add wave -noupdate -expand -group Bpred -expand -group RAS -expand /testbench/dut/hart/ifu/bpred/RASPredictor/memory
add wave -noupdate -expand -group Bpred -expand -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/popPC
Cleanup of the branch predictor flush and stall controls.
2021-03-12 20:57:53 +00:00
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrF
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
Updating the test bench to include a function radix. Not done.
2021-02-27 01:43:40 +00:00
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
Cleanup of the branch predictor flush and stall controls.
2021-03-12 20:57:53 +00:00
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
add wave -noupdate -group {Decode Stage} /testbench/InstrDName
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
fixed issue with BTB's valid bit not updating. There is still a problem is valid not ocurring in the correct clock cycle.
2021-03-24 01:06:45 +00:00
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rf
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ALUResultW
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags
add wave -noupdate -group alu -divider internals
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
Added FlushF to hazard unit. Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined. I will look this up and add it to the compiler.
2021-02-19 22:36:51 +00:00
add wave -noupdate /testbench/InstrFName
Added possibly working OSU test bench as a precursor to running a bp benchmark. Fixed a few bugs with the function radix.
2021-03-17 16:06:32 +00:00
add wave -noupdate -expand -group dcache /testbench/dut/hart/MemAdrM
add wave -noupdate -expand -group dcache /testbench/dut/hart/MemPAdrM
add wave -noupdate -expand -group dcache /testbench/dut/hart/WriteDataM
add wave -noupdate -expand -group dcache /testbench/dut/hart/dmem/MemRWM
Updating the test bench to include a function radix. Not done.
2021-02-27 01:43:40 +00:00
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2E
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RdE
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RdM
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RdW
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/MemReadE
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RegWriteM
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RegWriteW
add wave -noupdate -group Forward -color Thistle /testbench/dut/hart/ieu/fw/ForwardAE
add wave -noupdate -group Forward -color Thistle /testbench/dut/hart/ieu/fw/ForwardBE
add wave -noupdate -group Forward -color Thistle /testbench/dut/hart/ieu/fw/LoadStallD
Cleanup of the branch predictor flush and stall controls.
2021-03-12 20:57:53 +00:00
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/WriteDataE
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
Updating the test bench to include a function radix. Not done.
2021-02-27 01:43:40 +00:00
add wave -noupdate /testbench/dut/hart/ieu/dp/ALUResultM
fixed a whole bunch of bugs with the branch predictor. Still an issue with how PCNextF is not updated because the CPU is stalled.
2021-03-23 21:53:48 +00:00
add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF
Added possibly working OSU test bench as a precursor to running a bp benchmark. Fixed a few bugs with the function radix.
2021-03-17 16:06:32 +00:00
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF
add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE
add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM
add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCW
fixed issue with BTB's valid bit not updating. There is still a problem is valid not ocurring in the correct clock cycle.
2021-03-24 01:06:45 +00:00
add wave -noupdate -expand -group PCS -expand -group pcnextmux /testbench/dut/hart/ifu/PCNextF
add wave -noupdate -expand -group PCS -expand -group pcnextmux /testbench/dut/hart/ifu/PCNext0F
add wave -noupdate -expand -group PCS -expand -group pcnextmux /testbench/dut/hart/ifu/PCNext1F
Cleanup of the branch predictor flush and stall controls.
2021-03-12 20:57:53 +00:00
add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/FunctionAddr
Added possibly working OSU test bench as a precursor to running a bp benchmark. Fixed a few bugs with the function radix.
2021-03-17 16:06:32 +00:00
add wave -noupdate -group {function radix debug} -radix unsigned /testbench/functionRadix/function_radix/ProgramAddrIndex
Cleanup of the branch predictor flush and stall controls.
2021-03-12 20:57:53 +00:00
add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/reset
add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/ProgramLabelMapLineCount
add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/ProgramLabelMapLine
add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/ProgramLabelMapFP
add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/ProgramLabelMapFile
add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/ProgramAddrMapLineCount
add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/ProgramAddrMapLine
add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/ProgramAddrMapFP
add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/ProgramAddrMapFile
add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/pc
add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/FunctionAddr
add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/ProgramAddrIndex
add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/FunctionName
Simulation definitely shows the branch predictor counters and branch predictor don't work. :(
2021-03-23 19:04:58 +00:00
add wave -noupdate -expand -group {performance counters} /testbench/dut/hart/priv/csr/genblk1/counters/HPMCOUNTER
add wave -noupdate -expand -group {performance counters} /testbench/dut/hart/priv/csr/genblk1/counters/MHPMCOUNTERH
add wave -noupdate -expand -group {performance counters} /testbench/dut/hart/priv/csr/genblk1/counters/MCOUNTEN
add wave -noupdate -expand -group {performance counters} /testbench/dut/hart/priv/csr/genblk1/counters/MCOUNTINHIBIT_REGW
fixed issue with BTB's valid bit not updating. There is still a problem is valid not ocurring in the correct clock cycle.
2021-03-24 01:06:45 +00:00
add wave -noupdate /testbench/dut/hart/ifu/SelBPPredF
Wrote a bash script to generate custom modelsim radix which maps instruction addresses into human readable lables. Once combined with some simulation verilog this will display the current function in modelsim.
2021-02-18 04:20:28 +00:00
TreeUpdate [SetDefaultTree]
Fixed a bunch of bugs with the RAS.
2021-03-24 02:49:16 +00:00
WaveRestoreCursors {{Cursor 6} {12508605 ns} 0}
Added possibly working OSU test bench as a precursor to running a bp benchmark. Fixed a few bugs with the function radix.
2021-03-17 16:06:32 +00:00
quietly wave cursor active 1
Wrote a bash script to generate custom modelsim radix which maps instruction addresses into human readable lables. Once combined with some simulation verilog this will display the current function in modelsim.
2021-02-18 04:20:28 +00:00
configure wave -namecolwidth 250
Improve version of the function radix which does not cause the wave file rendering to slow down.
2021-03-11 23:12:21 +00:00
configure wave -valuecolwidth 229
Wrote a bash script to generate custom modelsim radix which maps instruction addresses into human readable lables. Once combined with some simulation verilog this will display the current function in modelsim.
2021-02-18 04:20:28 +00:00
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
Fixed a bunch of bugs with the RAS.
2021-03-24 02:49:16 +00:00
WaveRestoreZoom {0 ns} {16338232 ns}
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