Jordan Carlin b401decfca Fetch buffer passes regression!		2024-11-07 16:43:18 -08:00
..
cache	Updated email address authorship for my files.	2024-10-15 10:27:53 -05:00
ebu	Updated email address authorship for my files.	2024-10-15 10:27:53 -05:00
fpu	Fixed fmvp.d.x bug	2024-11-06 03:32:53 -08:00
generic	Updated email address authorship for my files.	2024-10-15 10:27:53 -05:00
hazard	Fetch buffer passes regression!	2024-11-07 16:43:18 -08:00
ieu	Remove outdated code	2024-09-23 06:06:26 -07:00
ifu	Fetch buffer passes regression!	2024-11-07 16:43:18 -08:00
lsu	Updated email address authorship for my files.	2024-10-15 10:27:53 -05:00
mdu	Unused signal cleanup	2024-06-18 08:15:48 -07:00
mmu	Revert "This is a better solution. It's closer to the original book HPTW FSM,"	2024-10-11 17:02:51 -05:00
privileged	Implemented mhpmevent[3:31] as read-only zero rather than illegal	2024-10-15 09:08:25 -07:00
rvvi	Updated email address authorship for my files.	2024-10-15 10:27:53 -05:00
uncore	Removed impossible condition in receive register logic.	2024-11-04 16:15:42 -06:00
wally	improved implementation, simulation running w/ few passes	2024-10-07 03:04:39 -07:00
cvw.sv	Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.	2024-07-24 12:47:50 -05:00