cvw/wally-pipelined/regression
Jarred Allen 6cda818f09 Merge branch 'cache2' into cache
Conflicts:
	wally-pipelined/testbench/testbench-imperas.sv
2021-03-30 13:32:33 -04:00
..
wave-dos Merge branch 'cache2' into cache 2021-03-30 13:32:33 -04:00
regression-wally.py regression: use busybear batch instead 2021-03-25 15:34:10 -04:00
sim-busybear busybear: add sim-busybear and sim-busybear-batch based on sim-wally 2021-03-01 21:01:15 +00:00
sim-busybear-batch busybear: make a second .do file with better optimization for command line mode 2021-03-08 19:35:00 +00:00
sim-wally Added test configurations 2021-01-25 11:28:43 -05:00
sim-wally-batch Fixed issue with sim-wally-batch. Are people still using this script? 2021-03-17 11:17:52 -05:00
sim-wally-rv32ic AHB bugfixes and sim waveview refactoring 2021-03-18 18:25:12 -04:00
wally-busybear-batch.do Converted branch predictor preloads to use system verilog rather than modelsim's load command. 2021-03-15 12:39:44 -05:00
wally-busybear.do Merge branch 'main' into cache 2021-03-30 12:55:01 -04:00
wally-coremark_bare.do Removed PCW and InstrW from ifu 2021-03-26 01:53:19 +05:30
wally-coremark.do Removed PCW and InstrW from ifu 2021-03-26 01:53:19 +05:30
wally-peripherals-signals.do refactored sim file 2021-03-05 14:25:16 -05:00
wally-peripherals.do Converted branch predictor preloads to use system verilog rather than modelsim's load command. 2021-03-15 12:39:44 -05:00
wally-pipelined-batch.do Condense the parallel and non-parallel wally-pipelined-batch.do files into one 2021-03-16 18:15:13 -04:00
wally-pipelined-ross.do Converted branch predictor preloads to use system verilog rather than modelsim's load command. 2021-03-15 12:39:44 -05:00
wally-pipelined.do rv64i linear control flow now working 2021-03-25 13:02:26 -04:00
wally-privileged.do Fix bugs with privileged tests 2021-03-25 14:06:05 -04:00
wave-all.do Removed PCW and InstrW from ifu 2021-03-26 01:53:19 +05:30
wave.do Removed PCW and InstrW from ifu 2021-03-26 01:53:19 +05:30