cvw/wally-pipelined/regression
2021-05-17 18:02:35 -04:00
..
wave-dos Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version 2021-05-17 16:48:51 -05:00
regression-wally.py Minor fixes in regression 2021-05-09 13:57:09 -04:00
run_sim.sh Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
sim-buildroot start to add buildroot testbench 2021-04-16 23:27:29 -04:00
sim-buildroot-batch start to add buildroot testbench 2021-04-16 23:27:29 -04:00
sim-busybear busybear: add sim-busybear and sim-busybear-batch based on sim-wally 2021-03-01 21:01:15 +00:00
sim-busybear-batch busybear: make a second .do file with better optimization for command line mode 2021-03-08 19:35:00 +00:00
sim-wally Added test configurations 2021-01-25 11:28:43 -05:00
sim-wally-batch Fixed issue with sim-wally-batch. Are people still using this script? 2021-03-17 11:17:52 -05:00
sim-wally-batch-muldiv Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version 2021-05-17 16:48:51 -05:00
sim-wally-batch-rv32ic fixed sim-wally-32ic 2021-04-08 13:40:16 -04:00
sim-wally-muldiv Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version 2021-05-17 16:48:51 -05:00
sim-wally-rv32ic fixed sim-wally-32ic 2021-04-08 13:40:16 -04:00
udiv.c Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version 2021-05-17 16:48:51 -05:00
vish_stacktrace.vstf Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version 2021-05-17 16:48:51 -05:00
wally-buildroot-batch.do do script refactor 2021-04-24 09:32:09 -04:00
wally-buildroot.do do script refactor 2021-04-24 09:32:09 -04:00
wally-busybear-batch.do Minor fixes in regression 2021-05-09 13:57:09 -04:00
wally-busybear.do Add mmu waves (commented) to busybear 2021-04-28 20:01:05 -04:00
wally-coremark_bare.do coremark print statment 2021-05-03 19:35:08 -04:00
wally-pipelined-batch-muldiv.do Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version 2021-05-17 16:48:51 -05:00
wally-pipelined-batch.do Condense the parallel and non-parallel wally-pipelined-batch.do files into one 2021-03-16 18:15:13 -04:00
wally-pipelined-muldiv.do Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version 2021-05-17 16:48:51 -05:00
wally-pipelined-ross.do Converted branch predictor preloads to use system verilog rather than modelsim's load command. 2021-03-15 12:39:44 -05:00
wally-pipelined.do do script refactor 2021-04-24 09:32:09 -04:00
wally-privileged.do Add medeleg tests 2021-04-29 15:02:36 -04:00
wave-all.do Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
wave.do fixed subtle typo in icache fsm. Was messing up hit spill hit. 2021-05-03 16:55:36 -05:00