David Harris 1c1acc467e Tweaked SPI to avoid breaking VCS, but the SCLK divider still doesn't produce the right frequency and SCLKenableEarly looks like it wouldn't work for SckDiv = 0		2024-10-26 02:01:09 -07:00
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cache	Updated email address authorship for my files.	2024-10-15 10:27:53 -05:00
ebu	Updated email address authorship for my files.	2024-10-15 10:27:53 -05:00
fpu	Issue #894: trap on floating-point ops with reserved rounding modes: detect Zfa flt	2024-07-25 09:09:13 -07:00
generic	Updated email address authorship for my files.	2024-10-15 10:27:53 -05:00
hazard	Merge branch 'rvvi'	2024-07-22 12:01:01 -05:00
ieu	Remove outdated code	2024-09-23 06:06:26 -07:00
ifu	Updated email address authorship for my files.	2024-10-15 10:27:53 -05:00
lsu	Updated email address authorship for my files.	2024-10-15 10:27:53 -05:00
mdu	Unused signal cleanup	2024-06-18 08:15:48 -07:00
mmu	Revert "This is a better solution. It's closer to the original book HPTW FSM,"	2024-10-11 17:02:51 -05:00
privileged	Implemented mhpmevent[3:31] as read-only zero rather than illegal	2024-10-15 09:08:25 -07:00
rvvi	Updated email address authorship for my files.	2024-10-15 10:27:53 -05:00
uncore	Tweaked SPI to avoid breaking VCS, but the SCLK divider still doesn't produce the right frequency and SCLKenableEarly looks like it wouldn't work for SckDiv = 0	2024-10-26 02:01:09 -07:00
wally	Merge branch 'main' of github.com:openhwgroup/cvw into spiboot	2024-08-06 17:09:39 -05:00
cvw.sv	Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.	2024-07-24 12:47:50 -05:00