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Author SHA1 Message Date
David Harris
708b914a65 Lint cleanup from wallypipeliendhart 2021-10-23 10:29:52 -07:00
David Harris
817795f619 Lint cleanup: ahblite, ifu, hart 2021-10-23 10:12:33 -07:00
David Harris
2abec36221 Lint cleanup 2021-10-23 09:58:52 -07:00
David Harris
6ae9aa7d80 lint cleanup: FPU and privileged 2021-10-23 09:41:24 -07:00
David Harris
80d2b9bc0d subword read and csrc lint cleanup 2021-10-23 09:29:15 -07:00
David Harris
0eabd0ecc2 FMA and CSRC lint cleanup 2021-10-23 09:20:24 -07:00
David Harris
5235e61d9e Lint cleanup 2021-10-23 09:06:21 -07:00
David Harris
bf3eb7b814 update scripts for handling src/*/* subdirectories 2021-10-23 08:54:29 -07:00
David Harris
7732d38c36 lint cleaning and moved files into subdirectories 2021-10-23 08:53:32 -07:00
David Harris
ff409d4fe7 Lint cleanup 2021-10-23 08:39:21 -07:00
David Harris
1b1317e6c3 hope I added logic declarations to divconv_pipe ok 2021-10-23 08:10:16 -07:00
James E. Stine
0e2efca490 Remove redundant logic value 2021-10-23 10:02:47 -05:00
David Harris
8b854bb1c2 Cleaned up LINT erors 2021-10-23 06:28:49 -07:00
David Harris
5142bfd624 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-23 06:15:49 -07:00
David Harris
3407b63c8a Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience. 2021-10-23 06:15:26 -07:00
Ross Thompson
6bad4058eb Merge branch 'main' into fpga 2021-10-22 16:09:16 -05:00
kipmacsaigoren
611c4733cf lowered number of paths to speed synth up and removed extra unnecessary report copying. 2021-10-22 15:25:11 -05:00
kipmacsaigoren
c2f4b49b15 removed reduntant definitions for FPU in MISA. 2021-10-22 15:18:25 -05:00
James E. Stine
a60e19dc3f Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking 2021-10-22 13:41:50 -05:00
Katherine Parry
00cc1e0c5c put the FMA priority encoders into their own module 2021-10-22 10:03:12 -07:00
James E. Stine
0e0a107a98 Get rid of lint warning - still need more testing though 2021-10-21 15:19:22 -05:00
James E. Stine
49721a169b Clean up some FPU and add pipelined fpdivsqrt to fpu.sv 2021-10-21 13:52:12 -05:00
James E. Stine
129ef03b2d Fix fpdivsqrt lint error on CPA for convergence 2021-10-20 17:46:13 -05:00
Ross Thompson
09dc3e1143 Merge branch 'main' into fpga 2021-10-20 16:24:55 -05:00
Ross Thompson
f4e64c2eaf Added debug signals to dcache. 2021-10-20 15:52:05 -05:00
David Harris
687703f0d8 removed .* from wallypipeliendsoc 2021-10-20 13:49:18 -07:00
davidharrishmc
923d03f657 Update README.md 2021-10-20 10:49:41 -07:00
kipmacsaigoren
742480d27d Fixed path to src and config files, added mdu timing reports 2021-10-20 12:41:14 -05:00
kipmacsaigoren
b2deedd4b4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-20 12:15:53 -05:00
kipmacsaigoren
f0cf8bf17e Removed historical outputs from repo 2021-10-20 12:15:40 -05:00
James E. Stine
7536e0a2ee Added pipelined version of fpdivsqrt as well as analysis of fpdivsqrt to cut multiplier down to 60bits. 2021-10-20 12:00:41 -05:00
David Harris
4aeadaacf0 moved coemark and testsBP to tests 2021-10-20 09:10:06 -07:00
David Harris
55fbafec74 moved imperas-riscv-tests to tests 2021-10-20 09:07:46 -07:00
David Harris
0e4f6392d6 Move tests into subdirectory and moved wavedrom out of project 2021-10-20 09:03:21 -07:00
David Harris
15e3b36a75 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-19 14:08:24 -07:00
David Harris
8747791bb8 radix 2 SRT checkin 2021-10-19 14:08:16 -07:00
bbracker
ca61d9b6b8 gitignore the addins folder because it contains external repos 2021-10-19 13:32:26 -07:00
James E. Stine
ed179b0bd9 Some more sanitization but will pass to legal to determine if okay on version - it is substantially different in some ways but not a legal expert on this 2021-10-19 12:09:43 -05:00
James E. Stine
b65a4bd040 Modify DW02_multp to properly list the correct number of bits at the output (i.e., 2*WIDTH + 2). 2021-10-19 11:58:06 -05:00
Ross Thompson
77a89c30de Fixed bug with the external memory region selection. 
Updated bios program to copy just 127MB to dram.
 2021-10-19 11:23:23 -05:00
David Harris
8d08ca6a1e Changed some flops to settable 2021-10-18 17:05:29 -07:00
David Harris
965946cae3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-18 16:54:08 -07:00
David Harris
df0b65e483 replaced flopenl with flopenr when clearing to 0 2021-10-18 16:53:18 -07:00
davidharrishmc
83af0740b5 Update README.md 2021-10-18 16:23:22 -07:00
David Harris
d0b9ebd2ef Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-18 15:44:31 -07:00
David Harris
47f7a5db9c Fixed multiplier and pointed arch tests to new path in addins 2021-10-18 15:43:59 -07:00
Ross Thompson
83a76ffb0c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-18 17:25:48 -05:00
Ross Thompson
d8d414665c fixed issues with dc shell not liking modules with parameters without default values. 2021-10-18 17:24:15 -05:00
davidharrishmc
b8a126f311 Update README.md 2021-10-18 13:43:10 -07:00
davidharrishmc
091d8550d0 Update README.md 2021-10-18 13:39:40 -07:00