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Remove redundant logic value

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James E. Stine 2021-10-23 10:02:47 -05:00
parent 5142bfd624
commit 0e2efca490
1 changed files with 0 additions and 2 deletions
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wally-pipelined/src/fpu/divconv_pipe.sv
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@ -66,8 +66,6 @@ module divconv_pipe (q1, qm1, qp1, q0, qm0, qp0, rega_out, regb_out, regc_out, r
logic [59:0] d2, n2;
logic [11:0] d3;
logic muxr_out, cout1, cout2, cout3, cout4, cout5, cout6, cout7;
// Check if exponent is odd for sqrt
// If exp_odd=1 and sqrt, then M/2 and use ia_addr=0 as IA
assign d2 = (exp_odd&op_type) ? {vss, d, 6'h0} : {d, 7'h0};