Ross Thompson
fd77022f73
No dcache now supported. Does not pass regression tests however.
2021-12-30 15:26:32 -06:00
Ross Thompson
bd531d1996
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-30 14:56:24 -06:00
Ross Thompson
59a38e3efd
Separated the icache from the bus fetching logic. I was able to share the same fsm between the lsu and ifu.
2021-12-30 14:56:17 -06:00
David Harris
451f37729f
Added names to generate blocks
2021-12-30 20:55:48 +00:00
Ross Thompson
9ea308b2d7
icache separated from bus fetch fsm. Does not work yet.
2021-12-30 14:23:05 -06:00
David Harris
91b8d7d2eb
erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-30 17:22:22 +00:00
David Harris
e084c8868f
Added wally-riscv-arch-test MMU tests and removed imperas MMU tests from regresssion
2021-12-30 17:22:18 +00:00
Ross Thompson
f3fe91eba1
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-30 11:01:22 -06:00
Ross Thompson
3803b9cd2d
Changed names of Icache signals.
2021-12-30 11:01:11 -06:00
David Harris
c1969ca142
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-30 16:49:36 +00:00
David Harris
da402f93cc
Fixed page table entreis so WALLY-MMU-SV32, SV39, SV48 now run
2021-12-30 16:46:19 +00:00
Ross Thompson
26ad3fc11f
Icache now works with any sized cache line a power of 2, greater than or equal to 32.
2021-12-30 10:37:57 -06:00
Ross Thompson
8d5c86e908
More name cleanup in caches.
2021-12-30 09:18:16 -06:00
Ross Thompson
e506957790
Updated lsu so it is possible to condictionally implement dcache or passthrough to ebu.
2021-12-29 22:24:37 -06:00
Ross Thompson
e640f3f4fb
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-29 21:39:57 -06:00
Ross Thompson
903547f25f
Removed WAdr from cacheway as it is redundant.
2021-12-29 21:39:43 -06:00
Ross Thompson
525c7120b4
Rename of dcache interface signals.
2021-12-29 21:26:15 -06:00
David Harris
c6f4a15bfb
Fixed generate statement name in csrm for buildroot regression
2021-12-30 03:01:21 +00:00
David Harris
75b8e1f68e
Fixed lint for RV32IC by handling PMP_ENTRIES = 0 in csrm, but may have broken buildroot.
2021-12-30 02:38:42 +00:00
David Harris
cca775e8a3
erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-30 02:25:48 +00:00
David Harris
26d6f8d51a
RV32ic tests running for simple machine with no privileged unit
2021-12-30 02:25:46 +00:00
Ross Thompson
00f90d8b25
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-29 20:18:06 -06:00
Ross Thompson
9e1f76baa0
Fixed lint issues with SDC.
2021-12-29 20:18:00 -06:00
David Harris
75c0c8ebea
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-30 00:53:44 +00:00
David Harris
866a5efc43
rv32i regression and linting
2021-12-30 00:53:39 +00:00
Katherine Parry
1d4ff095cf
all FCVT imperas tests pass
2021-12-30 00:19:40 +00:00
Ross Thompson
31d87d459e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-29 17:56:58 -06:00
Ross Thompson
fd1c4b7313
Added default to busfsm.
2021-12-29 17:53:24 -06:00
David Harris
07f34c8263
.gitmodule added dirty riscv-arch-test
2021-12-29 23:50:17 +00:00
David Harris
3fdaa0ab2c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-29 23:49:16 +00:00
Ross Thompson
87b7f80282
Moved lsu interlock fpm to separate module.
2021-12-29 17:40:24 -06:00
Ross Thompson
1955b6e740
Moved LSU Bus interface control path into it's own module.
2021-12-29 17:35:45 -06:00
Ross Thompson
56d86f4dd5
Moved LSU Bus interface control path into it's own module.
2021-12-29 17:12:29 -06:00
Ross Thompson
ac5746c721
Name cleanup in LSU.
2021-12-29 16:34:35 -06:00
Ross Thompson
aa227ce97c
Changed names of lsu address signals.
2021-12-29 15:03:34 -06:00
Ross Thompson
60f0339690
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-29 14:48:16 -06:00
Ross Thompson
e36a037afa
Added more generates around virtual memory and csrs in the lsu.
2021-12-29 14:48:09 -06:00
James E. Stine
2339e3a483
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-29 13:01:27 -06:00
James E. Stine
2e5b805b0a
Add configuration for IEEE 754 or non IEEE 754 per RISC-V guidelines
...
Katherine/James
2021-12-29 12:59:17 -06:00
David Harris
ea42025901
Fixed .gitignore
2021-12-29 18:58:36 +00:00
David Harris
b6dd0b110c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-29 18:53:13 +00:00
David Harris
57d32e58c6
Switched riscv-arch-test to current hash
2021-12-29 18:52:52 +00:00
Ross Thompson
995cfb1cf3
Cleaned up some names in dcache and lsu.
2021-12-29 11:21:44 -06:00
Ross Thompson
bc6e776609
Converted mux4 to mux3 in dcache.
2021-12-29 10:58:02 -06:00
Ross Thompson
5ebaeb5d90
Simplified the dcache to bus address generation.
2021-12-29 10:46:48 -06:00
Ross Thompson
15f1627a31
Fixed interrupt delay bug by reverting CommittedM changes.
2021-12-28 22:27:12 -06:00
Ross Thompson
a82af378e2
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-28 21:28:12 -06:00
Ross Thompson
29b3285c8e
Changed name of LSU's FetchCount to WordCount. This better reflex the dual usage as fetch and eviction counters.
...
Fixed bug with the uncached memory operations. The periph tests still do not pass. They enter into what seems an intentional infinite loop. Then a uart interrupt jumps into an ISR but the ISR returns back to the loop.
2021-12-28 21:28:03 -06:00
David Harris
c3bfa53db0
Added partially working MMU tests
2021-12-29 03:14:16 +00:00
Ross Thompson
67a33a80f9
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-28 20:22:36 -06:00
