mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-03 18:25:27 +00:00
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
This commit is contained in:
David Harris
commit
c1969ca142
@ -220,129 +220,127 @@ add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu
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add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusAdr
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add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusAck
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||||
add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusHWDATA
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WayHit
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM
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add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcache/dcachefsm/CurrState
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||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/WayHit
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMBlockWriteEnableM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWordWriteEnableM
|
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWayWriteEnable
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWordEnable
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMBlockWayWriteEnableM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SelAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/ReadDataBlockM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/MEM_VIRTMEM/SelReplayCPURequest
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrE
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/RAdr
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add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/FlushAdr
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add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/FlushWay
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add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimDirtyWay
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add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimTag
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add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/CacheableM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits}
|
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ValidBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty}
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData}
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||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable}
|
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ClearDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/VDWriteEnable}
|
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/RAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Valid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Valid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/LsuPAdrM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/RAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/dcache/FlushAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/FlushWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/VictimDirtyWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/VictimTag
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/CacheableM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/DCacheMemWriteData
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WriteWordEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetValid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ClearDirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/VDWriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/CacheTagMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/SetValid
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/ClearValid
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/SetDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/RAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/Valid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/Valid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/Valid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/WayHit}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/Valid}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/WayHit
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/ReadDataBlockWayMaskedM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/ReadDataWordM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimTag
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimDirtyWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimDirty
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuRWM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuAdrE
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuPAdrM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuAtomicM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/CacheableM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/FlushDCacheM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/DCacheStall
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/ReadDataWordM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/FinalWriteDataM
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCacheFetchLine
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCacheWriteLine
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/DCacheBusAck
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/FlushWay
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/dcache/WayHit
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/dcache/CacheHit
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheFetchLine
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheWriteLine
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheMemWriteData
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheBusAck
|
||||
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/FlushWay
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/VAdr
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/genblk1/tlb/PTE
|
||||
|
||||
39
wally-pipelined/src/cache/cacheway.sv
vendored
39
wally-pipelined/src/cache/cacheway.sv
vendored
@ -31,7 +31,6 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
|
||||
input logic reset,
|
||||
|
||||
input logic [$clog2(NUMLINES)-1:0] RAdr,
|
||||
input logic [$clog2(NUMLINES)-1:0] WAdr,
|
||||
input logic [`PA_BITS-1:0] PAdr,
|
||||
input logic WriteEnable,
|
||||
input logic VDWriteEnable,
|
||||
@ -64,7 +63,7 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
|
||||
logic [TAGLEN-1:0] VicDirtyWay;
|
||||
logic [TAGLEN-1:0] FlushThisWay;
|
||||
|
||||
logic [$clog2(NUMLINES)-1:0] RAdrD, WAdrD;
|
||||
logic [$clog2(NUMLINES)-1:0] RAdrD;
|
||||
logic SetValidD, ClearValidD;
|
||||
logic SetDirtyD, ClearDirtyD;
|
||||
logic WriteEnableD, VDWriteEnableD;
|
||||
@ -76,23 +75,20 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
|
||||
|
||||
generate
|
||||
for(words = 0; words < BLOCKLEN/`XLEN; words++) begin : word
|
||||
sram1rw #(.DEPTH(`XLEN),
|
||||
.WIDTH(NUMLINES))
|
||||
CacheDataMem(.clk(clk),
|
||||
.Addr(RAdr),
|
||||
.ReadData(ReadDataBlockWay[(words+1)*`XLEN-1:words*`XLEN] ),
|
||||
.WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]),
|
||||
.WriteEnable(WriteEnable & WriteWordEnable[words]));
|
||||
sram1rw #(.DEPTH(`XLEN), .WIDTH(NUMLINES))
|
||||
CacheDataMem(.clk(clk), .Addr(RAdr),
|
||||
.ReadData(ReadDataBlockWay[(words+1)*`XLEN-1:words*`XLEN] ),
|
||||
.WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]),
|
||||
.WriteEnable(WriteEnable & WriteWordEnable[words]));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
sram1rw #(.DEPTH(TAGLEN),
|
||||
.WIDTH(NUMLINES))
|
||||
sram1rw #(.DEPTH(TAGLEN), .WIDTH(NUMLINES))
|
||||
CacheTagMem(.clk(clk),
|
||||
.Addr(RAdr),
|
||||
.ReadData(ReadTag),
|
||||
.WriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]),
|
||||
.WriteEnable(TagWriteEnable));
|
||||
.Addr(RAdr),
|
||||
.ReadData(ReadTag),
|
||||
.WriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]),
|
||||
.WriteEnable(TagWriteEnable));
|
||||
|
||||
assign WayHit = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]);
|
||||
assign SelectedWay = SelFlush ? FlushWay :
|
||||
@ -101,10 +97,6 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
|
||||
|
||||
assign VictimDirtyWay = SelFlush ? FlushWay & Dirty & Valid :
|
||||
VictimWay & Dirty & Valid;
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
assign VictimTagWay = SelFlush & FlushWay ? ReadTag :
|
||||
VictimWay ? ReadTag : '0;
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
|
||||
assign VicDirtyWay = VictimWay ? ReadTag : '0;
|
||||
assign FlushThisWay = FlushWay ? ReadTag : '0;
|
||||
@ -116,13 +108,12 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
|
||||
ValidBits <= {NUMLINES{1'b0}};
|
||||
else if (InvalidateAll)
|
||||
ValidBits <= {NUMLINES{1'b0}};
|
||||
else if (SetValidD & (WriteEnableD | VDWriteEnableD)) ValidBits[WAdrD] <= 1'b1;
|
||||
else if (ClearValidD & (WriteEnableD | VDWriteEnableD)) ValidBits[WAdrD] <= 1'b0;
|
||||
else if (SetValidD & (WriteEnableD | VDWriteEnableD)) ValidBits[RAdrD] <= 1'b1;
|
||||
else if (ClearValidD & (WriteEnableD | VDWriteEnableD)) ValidBits[RAdrD] <= 1'b0;
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
RAdrD <= RAdr;
|
||||
WAdrD <= WAdr;
|
||||
SetValidD <= SetValid;
|
||||
ClearValidD <= ClearValid;
|
||||
WriteEnableD <= WriteEnable;
|
||||
@ -137,8 +128,8 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
|
||||
always_ff @(posedge clk) begin
|
||||
if (reset)
|
||||
DirtyBits <= {NUMLINES{1'b0}};
|
||||
else if (SetDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[WAdrD] <= 1'b1;
|
||||
else if (ClearDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[WAdrD] <= 1'b0;
|
||||
else if (SetDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[RAdrD] <= 1'b1;
|
||||
else if (ClearDirtyD & (WriteEnableD | VDWriteEnableD)) DirtyBits[RAdrD] <= 1'b0;
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
|
||||
34
wally-pipelined/src/cache/dcache.sv
vendored
34
wally-pipelined/src/cache/dcache.sv
vendored
@ -31,12 +31,10 @@ module dcache
|
||||
input logic CPUBusy,
|
||||
|
||||
// cpu side
|
||||
input logic [1:0] MemRWM,
|
||||
input logic [2:0] Funct3M,
|
||||
input logic [6:0] Funct7M,
|
||||
input logic [1:0] AtomicM,
|
||||
input logic [1:0] LsuRWM,
|
||||
input logic [1:0] LsuAtomicM,
|
||||
input logic FlushDCacheM,
|
||||
input logic [11:0] MemAdrE, // virtual address, but we only use the lower 12 bits.
|
||||
input logic [11:0] LsuAdrE, // virtual address, but we only use the lower 12 bits.
|
||||
input logic [`PA_BITS-1:0] LsuPAdrM, // physical address
|
||||
|
||||
input logic [`XLEN-1:0] FinalWriteDataM,
|
||||
@ -122,35 +120,25 @@ module dcache
|
||||
// Read Path CPU (IEU) side
|
||||
|
||||
mux3 #(INDEXLEN)
|
||||
AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||
AdrSelMux(.d0(LsuAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||
.d1(LsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||
.d2(FlushAdr),
|
||||
.s(SelAdrM),
|
||||
.y(RAdr));
|
||||
|
||||
cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN), .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN))
|
||||
MemWay[NUMWAYS-1:0](.clk,
|
||||
.reset,
|
||||
.RAdr,
|
||||
.WAdr(RAdr), // *** Reduce after addressing in icache also
|
||||
cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN),
|
||||
.OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN))
|
||||
MemWay[NUMWAYS-1:0](.clk, .reset, .RAdr,
|
||||
.PAdr(LsuPAdrM),
|
||||
.WriteEnable(SRAMWayWriteEnable),
|
||||
.VDWriteEnable(VDWriteEnableWay),
|
||||
.WriteWordEnable(SRAMWordEnable),
|
||||
.TagWriteEnable(SRAMBlockWayWriteEnableM),
|
||||
.WriteData(SRAMWriteData),
|
||||
.SetValid,
|
||||
.ClearValid,
|
||||
.SetDirty,
|
||||
.ClearDirty,
|
||||
.SelEvict,
|
||||
.VictimWay,
|
||||
.FlushWay,
|
||||
.SelFlush,
|
||||
.SetValid, .ClearValid, .SetDirty, .ClearDirty, .SelEvict,
|
||||
.VictimWay, .FlushWay, .SelFlush,
|
||||
.ReadDataBlockWayMasked(ReadDataBlockWayMaskedM),
|
||||
.WayHit,
|
||||
.VictimDirtyWay,
|
||||
.VictimTagWay,
|
||||
.WayHit, .VictimDirtyWay, .VictimTagWay,
|
||||
.InvalidateAll(1'b0));
|
||||
|
||||
generate
|
||||
@ -249,7 +237,7 @@ module dcache
|
||||
// controller
|
||||
|
||||
dcachefsm dcachefsm(.clk, .reset, .DCacheFetchLine, .DCacheWriteLine, .DCacheBusAck,
|
||||
.MemRWM, .AtomicM, .CPUBusy, .CacheableM, .IgnoreRequest,
|
||||
.LsuRWM, .LsuAtomicM, .CPUBusy, .CacheableM, .IgnoreRequest,
|
||||
.CacheHit, .VictimDirty, .DCacheStall, .DCacheCommittedM,
|
||||
.DCacheMiss, .DCacheAccess, .SelAdrM, .SetValid,
|
||||
.ClearValid, .SetDirty, .ClearDirty, .SRAMWordWriteEnableM,
|
||||
|
||||
20
wally-pipelined/src/cache/dcachefsm.sv
vendored
20
wally-pipelined/src/cache/dcachefsm.sv
vendored
@ -29,8 +29,8 @@ module dcachefsm
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
// inputs from IEU
|
||||
input logic [1:0] MemRWM,
|
||||
input logic [1:0] AtomicM,
|
||||
input logic [1:0] LsuRWM,
|
||||
input logic [1:0] LsuAtomicM,
|
||||
input logic FlushDCacheM,
|
||||
// hazard inputs
|
||||
input logic CPUBusy,
|
||||
@ -94,7 +94,7 @@ module dcachefsm
|
||||
|
||||
(* mark_debug = "true" *) statetype CurrState, NextState;
|
||||
|
||||
assign AnyCPUReqM = |MemRWM | (|AtomicM);
|
||||
assign AnyCPUReqM = |LsuRWM | (|LsuAtomicM);
|
||||
|
||||
// outputs for the performance counters.
|
||||
assign DCacheAccess = AnyCPUReqM & CacheableM & CurrState == STATE_READY;
|
||||
@ -156,7 +156,7 @@ module dcachefsm
|
||||
end
|
||||
|
||||
// amo hit
|
||||
else if(AtomicM[1] & (&MemRWM) & CacheableM & CacheHit) begin
|
||||
else if(LsuAtomicM[1] & (&LsuRWM) & CacheableM & CacheHit) begin
|
||||
SelAdrM = 2'b01;
|
||||
DCacheStall = 1'b0;
|
||||
|
||||
@ -172,7 +172,7 @@ module dcachefsm
|
||||
end
|
||||
end
|
||||
// read hit valid cached
|
||||
else if(MemRWM[1] & CacheableM & CacheHit) begin
|
||||
else if(LsuRWM[1] & CacheableM & CacheHit) begin
|
||||
DCacheStall = 1'b0;
|
||||
LRUWriteEn = 1'b1;
|
||||
|
||||
@ -185,7 +185,7 @@ module dcachefsm
|
||||
end
|
||||
end
|
||||
// write hit valid cached
|
||||
else if (MemRWM[0] & CacheableM & CacheHit) begin
|
||||
else if (LsuRWM[0] & CacheableM & CacheHit) begin
|
||||
SelAdrM = 2'b01;
|
||||
DCacheStall = 1'b0;
|
||||
SRAMWordWriteEnableM = 1'b1;
|
||||
@ -201,7 +201,7 @@ module dcachefsm
|
||||
end
|
||||
end
|
||||
// read or write miss valid cached
|
||||
else if((|MemRWM) & CacheableM & ~CacheHit) begin
|
||||
else if((|LsuRWM) & CacheableM & ~CacheHit) begin
|
||||
NextState = STATE_MISS_FETCH_WDV;
|
||||
DCacheStall = 1'b1;
|
||||
DCacheFetchLine = 1'b1;
|
||||
@ -244,11 +244,11 @@ module dcachefsm
|
||||
STATE_MISS_READ_WORD: begin
|
||||
SelAdrM = 2'b01;
|
||||
DCacheStall = 1'b1;
|
||||
if (MemRWM[0] & ~AtomicM[1]) begin // handles stores and amo write.
|
||||
if (LsuRWM[0] & ~LsuAtomicM[1]) begin // handles stores and amo write.
|
||||
NextState = STATE_MISS_WRITE_WORD;
|
||||
end else begin
|
||||
NextState = STATE_MISS_READ_WORD_DELAY;
|
||||
// delay state is required as the read signal MemRWM[1] is still high when we
|
||||
// delay state is required as the read signal LsuRWM[1] is still high when we
|
||||
// return to the ready state because the cache is stalling the cpu.
|
||||
end
|
||||
end
|
||||
@ -258,7 +258,7 @@ module dcachefsm
|
||||
SRAMWordWriteEnableM = 1'b0;
|
||||
SetDirty = 1'b0;
|
||||
LRUWriteEn = 1'b0;
|
||||
if(&MemRWM & AtomicM[1]) begin // amo write
|
||||
if(&LsuRWM & LsuAtomicM[1]) begin // amo write
|
||||
SelAdrM = 2'b01;
|
||||
if(CPUBusy) begin
|
||||
NextState = STATE_CPU_BUSY_FINISH_AMO;
|
||||
|
||||
26
wally-pipelined/src/cache/icache.sv
vendored
26
wally-pipelined/src/cache/icache.sv
vendored
@ -132,12 +132,9 @@ module icache
|
||||
|
||||
|
||||
|
||||
cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN), .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN),
|
||||
.DIRTY_BITS(0))
|
||||
MemWay[NUMWAYS-1:0](.clk,
|
||||
.reset,
|
||||
.RAdr(RAdr),
|
||||
.WAdr(PCTagF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
|
||||
cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN),
|
||||
.OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN), .DIRTY_BITS(0))
|
||||
MemWay[NUMWAYS-1:0](.clk, .reset, .RAdr,
|
||||
.PAdr(PCTagF),
|
||||
.WriteEnable(SRAMWayWriteEnable),
|
||||
.VDWriteEnable(1'b0),
|
||||
@ -145,19 +142,12 @@ module icache
|
||||
.TagWriteEnable(SRAMWayWriteEnable),
|
||||
.WriteData(ICacheMemWriteData),
|
||||
.SetValid(ICacheMemWriteEnable),
|
||||
.ClearValid(1'b0),
|
||||
.SetDirty(1'b0),
|
||||
.ClearDirty(1'b0),
|
||||
.SelEvict(1'b0),
|
||||
.ClearValid(1'b0), .SetDirty(1'b0), .ClearDirty(1'b0), .SelEvict(1'b0),
|
||||
.VictimWay,
|
||||
.FlushWay(1'b0),
|
||||
.SelFlush(1'b0),
|
||||
.ReadDataBlockWayMasked,
|
||||
.WayHit,
|
||||
.VictimDirtyWay(),
|
||||
.VictimTagWay(),
|
||||
.InvalidateAll(InvalidateICacheM)
|
||||
);
|
||||
.FlushWay(1'b0), .SelFlush(1'b0),
|
||||
.ReadDataBlockWayMasked, .WayHit,
|
||||
.VictimDirtyWay(), .VictimTagWay(),
|
||||
.InvalidateAll(InvalidateICacheM));
|
||||
|
||||
generate
|
||||
if(NUMWAYS > 1) begin
|
||||
|
||||
@ -88,8 +88,8 @@ module busfsm #(parameter integer WordCountThreshold,
|
||||
always_comb begin
|
||||
case(BusCurrState)
|
||||
STATE_BUS_READY: if(IgnoreRequest) BusNextState = STATE_BUS_READY;
|
||||
else if(LsuRWM[0] & ~CacheableM) BusNextState = STATE_BUS_UNCACHED_WRITE;
|
||||
else if(LsuRWM[1] & ~CacheableM) BusNextState = STATE_BUS_UNCACHED_READ;
|
||||
else if(LsuRWM[0] & (~CacheableM | ~`MEM_DCACHE)) BusNextState = STATE_BUS_UNCACHED_WRITE;
|
||||
else if(LsuRWM[1] & (~CacheableM | ~`MEM_DCACHE)) BusNextState = STATE_BUS_UNCACHED_READ;
|
||||
else if(DCacheFetchLine) BusNextState = STATE_BUS_FETCH;
|
||||
else if(DCacheWriteLine) BusNextState = STATE_BUS_WRITE;
|
||||
else BusNextState = STATE_BUS_READY;
|
||||
@ -134,5 +134,6 @@ module busfsm #(parameter integer WordCountThreshold,
|
||||
(BusCurrState == STATE_BUS_UNCACHED_READ |
|
||||
BusCurrState == STATE_BUS_UNCACHED_READ_DONE |
|
||||
BusCurrState == STATE_BUS_UNCACHED_WRITE |
|
||||
BusCurrState == STATE_BUS_UNCACHED_WRITE_DONE);
|
||||
BusCurrState == STATE_BUS_UNCACHED_WRITE_DONE) |
|
||||
~`MEM_DCACHE; // if no dcache always select uncachedadr.
|
||||
endmodule
|
||||
|
||||
@ -100,7 +100,7 @@ module lsu
|
||||
logic [2:0] LsuFunct3M;
|
||||
logic [1:0] LsuAtomicM;
|
||||
logic [`PA_BITS-1:0] PreLsuPAdrM, LocalLsuBusAdr;
|
||||
logic [11:0] LsuAdrE, DCacheAdrE;
|
||||
logic [11:0] PreLsuAdrE, LsuAdrE;
|
||||
logic CPUBusy;
|
||||
logic MemReadM;
|
||||
logic DCacheStall;
|
||||
@ -148,7 +148,7 @@ module lsu
|
||||
mux2 #(2) rwmux(MemRWM, {HPTWRead, 1'b0}, SelHPTW, PreLsuRWM);
|
||||
mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LsuFunct3M);
|
||||
mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LsuAtomicM);
|
||||
mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, LsuAdrE);
|
||||
mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, PreLsuAdrE);
|
||||
mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, PreLsuPAdrM);
|
||||
|
||||
// always block interrupts when using the hardware page table walker.
|
||||
@ -163,13 +163,13 @@ module lsu
|
||||
assign DTLBStorePageFaultM = DTLBPageFaultM & PreLsuRWM[0];
|
||||
|
||||
// When replaying CPU memory request after PTW select the IEUAdrM for correct address.
|
||||
assign DCacheAdrE = SelReplayCPURequest ? IEUAdrM[11:0] : LsuAdrE;
|
||||
assign LsuAdrE = SelReplayCPURequest ? IEUAdrM[11:0] : PreLsuAdrE;
|
||||
|
||||
end // if (`MEM_VIRTMEM)
|
||||
else begin
|
||||
assign InterlockStall = 1'b0;
|
||||
|
||||
assign DCacheAdrE = LsuAdrE;
|
||||
assign LsuAdrE = PreLsuAdrE;
|
||||
assign SelHPTW = 1'b0;
|
||||
assign IgnoreRequest = 1'b0;
|
||||
|
||||
@ -181,7 +181,7 @@ module lsu
|
||||
assign PreLsuRWM = MemRWM;
|
||||
assign LsuFunct3M = Funct3M;
|
||||
assign LsuAtomicM = AtomicM;
|
||||
assign LsuAdrE = IEUAdrE[11:0];
|
||||
assign PreLsuAdrE = IEUAdrE[11:0];
|
||||
assign PreLsuPAdrM = IEUAdrExtM;
|
||||
assign CPUBusy = StallW;
|
||||
|
||||
@ -274,10 +274,10 @@ module lsu
|
||||
// 2. cache `MEM_DCACHE
|
||||
// 3. wire pass-through
|
||||
|
||||
localparam integer WORDSPERLINE = `DCACHE_BLOCKLENINBITS/`XLEN;
|
||||
localparam integer WORDSPERLINE = `MEM_DCACHE ? `DCACHE_BLOCKLENINBITS/`XLEN : `XLEN/8;
|
||||
localparam integer LOGWPL = $clog2(WORDSPERLINE);
|
||||
localparam integer BLOCKLEN = `DCACHE_BLOCKLENINBITS;
|
||||
localparam integer WordCountThreshold = WORDSPERLINE - 1;
|
||||
localparam integer BLOCKLEN = `MEM_DCACHE ? `DCACHE_BLOCKLENINBITS : `XLEN;
|
||||
localparam integer WordCountThreshold = `MEM_DCACHE ? WORDSPERLINE - 1 : 0;
|
||||
|
||||
localparam integer BLOCKBYTELEN = BLOCKLEN/8;
|
||||
localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN);
|
||||
@ -287,7 +287,7 @@ module lsu
|
||||
logic [`XLEN-1:0] FinalAMOWriteDataM, FinalWriteDataM;
|
||||
(* mark_debug = "true" *) logic [`XLEN-1:0] PreLsuBusHWDATA;
|
||||
logic [`XLEN-1:0] ReadDataWordM;
|
||||
logic [`DCACHE_BLOCKLENINBITS-1:0] DCacheMemWriteData;
|
||||
logic [BLOCKLEN-1:0] DCacheMemWriteData;
|
||||
|
||||
// keep
|
||||
logic [`XLEN-1:0] ReadDataWordMuxM;
|
||||
@ -295,7 +295,7 @@ module lsu
|
||||
|
||||
|
||||
logic [`PA_BITS-1:0] DCacheBusAdr;
|
||||
logic [`XLEN-1:0] ReadDataBlockSetsM [(`DCACHE_BLOCKLENINBITS/`XLEN)-1:0];
|
||||
logic [`XLEN-1:0] ReadDataBlockSetsM [WORDSPERLINE-1:0];
|
||||
|
||||
|
||||
|
||||
@ -305,34 +305,36 @@ module lsu
|
||||
|
||||
logic SelUncachedAdr;
|
||||
|
||||
|
||||
dcache dcache(.clk, .reset, .CPUBusy,
|
||||
.MemRWM(LsuRWM),
|
||||
.Funct3M(LsuFunct3M),
|
||||
.Funct7M, .FlushDCacheM,
|
||||
.AtomicM(LsuAtomicM),
|
||||
.MemAdrE(DCacheAdrE),
|
||||
.LsuPAdrM,
|
||||
.FinalWriteDataM, .ReadDataWordM, .DCacheStall,
|
||||
.DCacheMiss, .DCacheAccess, .IgnoreRequest,
|
||||
.CacheableM(CacheableM),
|
||||
.DCacheCommittedM,
|
||||
.DCacheBusAdr,
|
||||
.ReadDataBlockSetsM,
|
||||
.DCacheMemWriteData,
|
||||
.DCacheFetchLine,
|
||||
.DCacheWriteLine,
|
||||
.DCacheBusAck
|
||||
);
|
||||
generate
|
||||
if(`MEM_DCACHE) begin : dcache
|
||||
dcache dcache(.clk, .reset, .CPUBusy,
|
||||
.LsuRWM, .FlushDCacheM, .LsuAtomicM, .LsuAdrE, .LsuPAdrM,
|
||||
.FinalWriteDataM, .ReadDataWordM, .DCacheStall,
|
||||
.DCacheMiss, .DCacheAccess,
|
||||
.IgnoreRequest, .CacheableM, .DCacheCommittedM,
|
||||
.DCacheBusAdr, .ReadDataBlockSetsM, .DCacheMemWriteData,
|
||||
.DCacheFetchLine, .DCacheWriteLine,.DCacheBusAck);
|
||||
end else begin : passthrough
|
||||
assign ReadDataWordM = 0;
|
||||
assign DCacheStall = 0;
|
||||
assign DCacheMiss = 1;
|
||||
assign DCacheAccess = CacheableM;
|
||||
assign DCacheCommittedM = 0;
|
||||
assign DCacheWriteLine = 0;
|
||||
assign DCacheFetchLine = 0;
|
||||
assign DCacheBusAdr = 0;
|
||||
assign ReadDataBlockSetsM[0] = 0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
|
||||
// sub word selection for read and writes and optional amo alu.
|
||||
// select between dcache and direct from the BUS. Always selected if no dcache.
|
||||
mux2 #(`XLEN) UnCachedDataMux(.d0(ReadDataWordM),
|
||||
.d1(DCacheMemWriteData[`XLEN-1:0]),
|
||||
.s(SelUncachedAdr),
|
||||
.y(ReadDataWordMuxM));
|
||||
|
||||
// sub word selection for read and writes and optional amo alu.
|
||||
// finally swr
|
||||
subwordread subwordread(.ReadDataWordMuxM,
|
||||
.LsuPAdrM(LsuPAdrM[2:0]),
|
||||
@ -348,15 +350,15 @@ module lsu
|
||||
end else
|
||||
assign FinalAMOWriteDataM = WriteDataM;
|
||||
endgenerate
|
||||
|
||||
|
||||
// this might only get instantiated if there is a dcache or dtim.
|
||||
// There is a copy in the ebu.
|
||||
subwordwrite subwordwrite(.HRDATA(ReadDataWordM),
|
||||
.HADDRD(LsuPAdrM[2:0]),
|
||||
.HSIZED({LsuFunct3M[2], 1'b0, LsuFunct3M[1:0]}),
|
||||
.HWDATAIN(FinalAMOWriteDataM),
|
||||
.HWDATA(FinalWriteDataM));
|
||||
|
||||
|
||||
|
||||
// Bus Side logic
|
||||
// register the fetch data from the next level of memory.
|
||||
// This register should be necessary for timing. There is no register in the uncore or
|
||||
@ -373,8 +375,6 @@ module lsu
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
|
||||
assign LocalLsuBusAdr = SelUncachedAdr ? LsuPAdrM : DCacheBusAdr ;
|
||||
assign LsuBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLsuBusAdr;
|
||||
assign PreLsuBusHWDATA = ReadDataBlockSetsM[WordCount];
|
||||
|
||||
@ -243,6 +243,7 @@ logic [3:0] dummy;
|
||||
/* verilator lint_off INFINITELOOP */
|
||||
while (signature[i] !== 'bx) begin
|
||||
//$display("signature[%h] = %h", i, signature[i]);
|
||||
// *** have to figure out how to exclude shadowram when not using a dcache.
|
||||
if (signature[i] !== dut.uncore.ram.ram.RAM[testadr+i] &&
|
||||
(signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
|
||||
if (signature[i+4] !== 'bx || signature[i] !== 32'hFFFFFFFF) begin
|
||||
@ -309,11 +310,12 @@ logic [3:0] dummy;
|
||||
dut.hart.ieu.dp.regf.a3 == 3 &&
|
||||
dut.hart.ieu.dp.regf.wd3 == 1)) ||
|
||||
(dut.hart.ifu.InstrM == 32'h6f || dut.hart.ifu.InstrM == 32'hfc32a423 || dut.hart.ifu.InstrM == 32'hfc32a823) && dut.hart.ieu.c.InstrValidM;
|
||||
|
||||
|
||||
// **** Fix when the check in the shadow ram is fixed.
|
||||
DCacheFlushFSM DCacheFlushFSM(.clk(clk),
|
||||
.reset(reset),
|
||||
.start(DCacheFlushStart),
|
||||
.done(DCacheFlushDone));
|
||||
.reset(reset),
|
||||
.start(DCacheFlushStart),
|
||||
.done(DCacheFlushDone));
|
||||
|
||||
|
||||
generate
|
||||
@ -363,10 +365,10 @@ module DCacheFlushFSM
|
||||
input logic start,
|
||||
output logic done);
|
||||
|
||||
localparam integer numlines = testbench.dut.hart.lsu.dcache.NUMLINES;
|
||||
localparam integer numways = testbench.dut.hart.lsu.dcache.NUMWAYS;
|
||||
localparam integer blockbytelen = testbench.dut.hart.lsu.dcache.BLOCKBYTELEN;
|
||||
localparam integer numwords = testbench.dut.hart.lsu.dcache.BLOCKLEN/`XLEN;
|
||||
localparam integer numlines = testbench.dut.hart.lsu.dcache.dcache.NUMLINES;
|
||||
localparam integer numways = testbench.dut.hart.lsu.dcache.dcache.NUMWAYS;
|
||||
localparam integer blockbytelen = testbench.dut.hart.lsu.dcache.dcache.BLOCKBYTELEN;
|
||||
localparam integer numwords = testbench.dut.hart.lsu.dcache.dcache.BLOCKLEN/`XLEN;
|
||||
localparam integer lognumlines = $clog2(numlines);
|
||||
localparam integer logblockbytelen = $clog2(blockbytelen);
|
||||
localparam integer lognumways = $clog2(numways);
|
||||
@ -392,10 +394,10 @@ module DCacheFlushFSM
|
||||
.logblockbytelen(logblockbytelen))
|
||||
copyShadow(.clk,
|
||||
.start,
|
||||
.tag(testbench.dut.hart.lsu.dcache.MemWay[way].CacheTagMem.StoredData[index]),
|
||||
.valid(testbench.dut.hart.lsu.dcache.MemWay[way].ValidBits[index]),
|
||||
.dirty(testbench.dut.hart.lsu.dcache.MemWay[way].DirtyBits[index]),
|
||||
.data(testbench.dut.hart.lsu.dcache.MemWay[way].word[cacheWord].CacheDataMem.StoredData[index]),
|
||||
.tag(testbench.dut.hart.lsu.dcache.dcache.MemWay[way].CacheTagMem.StoredData[index]),
|
||||
.valid(testbench.dut.hart.lsu.dcache.dcache.MemWay[way].ValidBits[index]),
|
||||
.dirty(testbench.dut.hart.lsu.dcache.dcache.MemWay[way].DirtyBits[index]),
|
||||
.data(testbench.dut.hart.lsu.dcache.dcache.MemWay[way].word[cacheWord].CacheDataMem.StoredData[index]),
|
||||
.index(index),
|
||||
.cacheWord(cacheWord),
|
||||
.CacheData(CacheData[way][index][cacheWord]),
|
||||
|
||||
Loading…
Reference in New Issue
Block a user