mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-03 18:25:27 +00:00
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
This commit is contained in:
commit
31d87d459e
5
.gitignore
vendored
5
.gitignore
vendored
@ -8,6 +8,7 @@ __pycache__/
|
||||
|
||||
#External repos
|
||||
addins
|
||||
addins/riscv-arch-test/Makefile.include
|
||||
|
||||
#vsim work files to ignore
|
||||
transcript
|
||||
@ -43,3 +44,7 @@ fpga/generator/WallyFPGA*
|
||||
fpga/generator/reports/
|
||||
fpga/generator/*.log
|
||||
fpga/generator/*.jou
|
||||
*.objdump*
|
||||
*.signature.output
|
||||
examples/asm/sumtest/sumtest
|
||||
|
||||
|
1
.gitmodules
vendored
1
.gitmodules
vendored
@ -4,6 +4,7 @@
|
||||
[submodule "addins/riscv-arch-test"]
|
||||
path = addins/riscv-arch-test
|
||||
url = https://github.com/riscv-non-isa/riscv-arch-test
|
||||
ignore = dirty
|
||||
[submodule "addins/imperas-riscv-tests"]
|
||||
path = addins/imperas-riscv-tests
|
||||
url = https://github.com/riscv-ovpsim/imperas-riscv-tests
|
||||
|
Loading…
Reference in New Issue
Block a user