Rose Thompson
fd032a7e10
Draft implementation of synth rvvi.
2024-01-24 15:06:13 -06:00
Rose Thompson
0babb011c2
Synthesizable rvvi tracer output G/FPRs.
2024-01-23 16:27:50 -06:00
Rose Thompson
cacbcb6fcf
Created the basic synthesizable wally tracer for fpga.
2024-01-23 16:16:29 -06:00
Rose Thompson
d5bbb5ea27
Merge branch 'main' of https://github.com/openhwgroup/cvw
2024-01-23 14:37:11 -06:00
David Harris
cb597d2c85
Merge pull request #592 from jordancarlin/main
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Coverage improvements
2024-01-22 09:56:35 -08:00
Jordan Carlin
0c13e14bbf
coverage improvements for mret when mpp = 3; update imperas config
2024-01-22 09:52:58 -08:00
Jordan Carlin
4936496bb9
fix sfence.inval.ir and sret coverage from previous PR
2024-01-22 08:58:31 -08:00
David Harris
788e3e16a1
Merge pull request #589 from kevindkim723/shiftcorrectiondebug
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more shiftcorrection bug fixes
2024-01-21 10:15:15 -08:00
Kevin Kim
1459943a75
more shiftcorrection bug fixes
2024-01-21 10:08:48 -08:00
David Harris
1b5d254031
Merge pull request #588 from kevindkim723/shiftcorrectiondebug
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CORRSHIFTSZ Signal Bug fix
2024-01-21 08:32:10 -08:00
Kevin Kim
991f1494d3
Merge branch 'openhwgroup:main' into shiftcorrectiondebug
2024-01-21 08:27:33 -08:00
Kevin Kim
3241802441
fixed bug in CORRSHIFTSZ param
2024-01-21 08:25:17 -08:00
Rose Thompson
68105e522d
Merge pull request #584 from davidharrishmc/dev
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Zfa partial support, coverage, etc.
2024-01-20 23:40:04 -06:00
David Harris
9260d3c424
Add Zfh support to imperas.ic, use Zicond in riscof now that it is fixed in riscv-arch-test
2024-01-18 22:46:07 -08:00
David Harris
13de147c7e
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-01-18 22:12:07 -08:00
David Harris
77270bc63d
Merge pull request #583 from jordancarlin/main
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Privilege coverage improvements
2024-01-18 22:11:29 -08:00
David Harris
9614913e8f
Changed CoreMark maiefile to rv64im
2024-01-18 22:10:20 -08:00
David Harris
17c9be7695
Cleanup typos, remove Zicond from riscof until it is working
2024-01-18 21:36:52 -08:00
David Harris
eb8ab3fae2
EBU coverage exclusion
2024-01-18 21:30:59 -08:00
David Harris
f06f681dbd
CoreMark displays StoreStalls
2024-01-18 21:30:39 -08:00
Jordan Carlin
82d9467eea
Add coverage of FIOM in different privelege modes
2024-01-18 19:29:16 -08:00
Jordan Carlin
12b2baff82
add coverage of sfence.inval.ir instruction and fix sret coverage
2024-01-18 17:33:59 -08:00
David Harris
911b400af2
Fault on misaligned AMO
2024-01-18 13:13:56 -08:00
Rose Thompson
4c2ba2b0b4
Added StoreStall back to csrc.
2024-01-18 14:43:34 -06:00
Rose Thompson
81d006536a
Lint passes with 32-bit no D$, but many regressions fail.
2024-01-18 09:48:44 -06:00
David Harris
d5e102d520
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-01-18 07:38:25 -08:00
David Harris
f986f53fc2
Merge pull request #580 from ross144/main
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Fixes remaining issues with issue #405 . Virtual memory now works without d$.
2024-01-18 07:37:57 -08:00
Rose Thompson
ff6bb3be0c
Fixed another bug with virtual memory and no caches.
2024-01-18 09:29:52 -06:00
Rose Thompson
e8474373e4
Fixed it so Virtual Memory work without a D$.
2024-01-18 09:18:17 -06:00
David Harris
b736d1971f
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2024-01-17 17:50:47 -08:00
David Harris
7069a90cb1
Merge pull request #579 from naichewa/main
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fixed SPI tests failing when no I$ disabled
2024-01-17 17:50:43 -08:00
naichewa
8b60992e72
fixed SPI tests failing when no icache
2024-01-17 14:38:11 -08:00
David Harris
74b242ce5c
Partial implementation of fcvtmod.w.d; flags disagree in one case where Sail might be wrong, and result 134 is wrong because of overflow
2024-01-17 12:25:06 -08:00
Rose Thompson
2d3dc55986
Fixed bug. After I$ invalidated. If the pipelined wasn't stalled the I$ still output the old instruction on the next cycle. Now the I$ ensure that invalidation leads to the next cycle not hitting.
2024-01-17 12:19:10 -06:00
David Harris
4cfc86140c
Zfa fmvh complete and passing tests:
2024-01-17 06:18:00 -08:00
David Harris
07e7e02241
Coded Zfa fmvp but no tests exist
2024-01-16 21:26:42 -08:00
David Harris
8654375f26
Zfa fminm/fmaxm/fltq/fleq implemented and tested
2024-01-16 20:03:54 -08:00
David Harris
9d57002c07
Zfa fli support working for F and D (add fli.sv module)
2024-01-16 17:27:59 -08:00
David Harris
0588d611ea
Zfa fli support working for F and D
2024-01-16 17:27:40 -08:00
David Harris
29eba93bfa
Path to new Questa
2024-01-16 17:26:46 -08:00
Rose Thompson
ed0f0d924b
Merge pull request #577 from davidharrishmc/dev
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Zfh fix and typo corrections
2024-01-16 14:23:23 -06:00
David Harris
60e09965d5
Enabled Zfh support in rv64gc
2024-01-16 11:14:43 -08:00
David Harris
846a0c4d50
Check fma operations don't support H precision
2024-01-16 11:12:06 -08:00
David Harris
1a77c08f6e
Fixed issues 575 and 477 about FPU tests failing when Zfh = 1.
2024-01-16 10:46:44 -08:00
David Harris
dcd40c6be7
Fixed spelling of output
2024-01-16 10:27:31 -08:00
David Harris
abecc98563
Fixed spelling of precision
2024-01-16 10:26:00 -08:00
David Harris
0c331e7828
Merge pull request #576 from ross144/main
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Fixes some but not all of the Issue #405 bugs. Fixes non-cached atomics, zifence when there is no dcache, and more serious bug with compressedF not supressed on the last cycle of a bus fetch.
2024-01-16 10:03:02 -08:00
Rose Thompson
ff5554ca61
Atomics work correctly without a d cache.
2024-01-16 10:43:20 -06:00
David Harris
bb3a7850c4
Simplified floating-point parameters in config-shared
2024-01-15 17:48:41 -08:00
Rose Thompson
dfe5ef4427
Added logic for the non-cache atomics.
2024-01-15 17:47:17 -06:00
