Jacob Pease
48a8dc7738
Added SPDX header to probe script.
2023-08-16 13:05:37 -05:00
Jacob Pease
3477f177ac
Fixed bug caused by errant tab size in probe script.
2023-08-16 12:20:08 -05:00
Jacob Pease
4cba4cb657
Added probe script to generate a single probe for the fpga.
2023-08-16 12:12:31 -05:00
Jacob Pease
87a6ad5a87
Removed non-existent SDC dependency from VCU targets in FPGA Makefile.
2023-07-27 15:01:20 -05:00
Jacob Pease
8b97d323e0
Fixed GPIO pin names in fpgaTop.v
2023-07-25 20:57:04 -05:00
Ross Thompson
717833b11a
Removed all old references to the old flash card controller.
...
Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
2023-07-24 15:45:57 -05:00
Ross Thompson
fd187e9ee6
Merge branch 'main' of github.com:ross144/cvw
2023-07-24 10:47:05 -05:00
Ross Thompson
d239b0649e
Improved timing constraints for arty a7 to push clock speed to 20Mhz.
2023-07-24 10:46:49 -05:00
Ross Thompson
6099b0e763
Fixed bugs in boot and new flash card merge. Works with arty a7 now.
2023-07-22 15:52:25 -05:00
Ross Thompson
6e17cfba03
At least it simulates and gets through fpga elaboration.
2023-07-21 18:40:26 -05:00
Ross Thompson
3eeecd2f27
Merge branch 'boot' into mergeBoot
...
Merges Jacob's new sdc controller into wally.
2023-07-21 17:43:45 -05:00
Ross Thompson
37078f3d9b
Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card.
2023-07-21 13:06:27 -05:00
Jacob Pease
36785848a5
Working new boot process. Buildroot package for sdc.
2023-07-20 14:15:59 -05:00
Ross Thompson
7873d26678
Fixed a bunch of timing constraints for the arty a7 board.
2023-07-19 17:08:16 -05:00
Ross Thompson
bae5359c6b
Fixed typo in fpga top for arty a7.
2023-07-19 11:37:29 -05:00
Ross Thompson
2854452ecc
Removed all old configuration files.
2023-07-19 10:28:54 -05:00
Ross Thompson
3bf2b35704
Wow. The newest version of Vivado does not like the enums as parameters.
...
The solution is simple. I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
2023-07-18 15:07:10 -05:00
Ross Thompson
5ce4ac963f
Updated arty a7 fpga top.
2023-07-17 15:55:57 -05:00
Jacob Pease
142ec857ed
Modified bootloader to access GUID partitions. SDC interrupt to PLIC.
...
Since writing an SD card image generation script, the bootloader
needed to be altered to access individual binaries from specific
partitions. A new file, gpt.c with it's header gpt.h, have been added
to the bootloader to facilitate this.
The SDC has been added to the device tree for the VCU108
board. Additionally the SDC interrupt signal was added to the PLIC
node in the device tree. The PLIC itself was modified to accept the
SDC interrupt signal.
2023-07-14 13:36:44 -05:00
Ross Thompson
4b3b590f21
Fpga does not correctly boot linux. I think the solution here is to revert out all substantive changes except for parameterization and then add them back in one at a time. This is necessary because the parameterization is not completed in one contiguous group of commits.
2023-06-22 12:55:49 -05:00
Ross Thompson
626a918668
FPGA updates.
2023-06-20 11:11:34 -05:00
Ross Thompson
25103176a0
Updated fpga wave config.
2023-06-19 12:28:30 -05:00
Ross Thompson
8242544efa
Updated fpga wally wrapper to work with the ILA.
2023-06-19 12:15:48 -05:00
Ross Thompson
24b8c6c391
I think the fpga is building again, but the debugger script needs to be updated. For some reason the nets are not present despite being marked debug.
2023-06-16 17:00:27 -05:00
Ross Thompson
4bee446cad
Vivado requires an intermediate wrapper file for parameterization.
2023-06-16 16:30:14 -05:00
Ross Thompson
2f35bec970
FPGA synthesis is broken. This commit moves closer to fixing the issues causes by parameterization.
2023-06-16 15:40:13 -05:00
Jacob Pease
2ad9c72acc
The Vivado-RISC-V SDC works. Wally is now booting through it.
2023-05-26 15:42:33 -05:00
Ross Thompson
86de36b6ce
FPGA makefile update.
2023-04-25 16:24:26 -05:00
Ross Thompson
d513956bb9
Updated fpga Makefile to work with both the Arty and VCU platforms.
2023-04-21 11:08:35 -05:00
Ross Thompson
a6903ac5f3
Yeah We boot linux on the arty a7!
2023-04-19 11:17:33 -05:00
Ross Thompson
c463bd8cdd
Fixed the reset for Arty A7 and now partially boots. Copies flash card to dram.
...
but the data is wrong.
2023-04-19 10:35:18 -05:00
Ross Thompson
d783456746
Found the first issue. the axi clock converter was stuck in reset because the polarity was reversed.
2023-04-18 17:45:41 -05:00
Ross Thompson
bb4ebd9b61
More debug stuff.
2023-04-18 16:00:10 -05:00
Ross Thompson
667524efcb
Added more signals to debugger in hopes I can figure out why the mig is not responding.
2023-04-18 15:51:52 -05:00
Jacob Pease
53de2bf782
AHB triggers write, but AXI side doesn't update.
2023-04-18 15:23:22 -05:00
Ross Thompson
2df6c6cb0f
It's almost working.
2023-04-18 14:24:59 -05:00
Ross Thompson
ac95087042
Improved constraints and set ddr3 voltage to correct 1.35V. This voltage is only for synthesis. However I'm concerned because the gui did not let me select 1.35V.
2023-04-17 20:05:59 -05:00
Ross Thompson
dd7f5310e4
Fixed timing constraint issue.
2023-04-17 19:53:43 -05:00
Ross Thompson
00c61fc5b3
Found the DDR3 memory is not ready when issuing the first store.
2023-04-17 19:33:13 -05:00
Ross Thompson
8bebc56b56
Finally we are building the fpga and can view the ila. we are getting out of reset, but we are stuck at PCM = 10b8.
2023-04-17 18:39:25 -05:00
Ross Thompson
8377ff8c51
Dang. Looks like the reset button on the arty a7 is actually resetn. I wish they'd named it that way.
2023-04-17 16:37:18 -05:00
Ross Thompson
96781e0b2a
Yay! We now have a functional ila and the uart connection on the pc side works. However the CPU is stuck in reset. Not really sure what's going on there.
2023-04-17 16:00:02 -05:00
Ross Thompson
fad0366d26
Adding in the ILA to the arty a7.
2023-04-17 14:54:10 -05:00
Ross Thompson
0be81fdfc8
Lowered arty a7 clock frequency to 15Mhz to meet timing. can probalby go faster.
2023-04-17 12:16:31 -05:00
Ross Thompson
a7a362f82e
Finally got the arty a7 to build.
2023-04-17 11:54:22 -05:00
Ross Thompson
9070b4adf5
OMG. the ddr3 has it's own mmcm (pll) which had incorreclty specified the input clock period as 3000 ps rather than 6000 ps so the pll was running at twice the speed. I speed the whole weekend on this. :(
2023-04-17 11:10:19 -05:00
Ross Thompson
5da5b76449
Fixed more issues with arty a7 constarints.
2023-04-16 13:25:02 -05:00
Ross Thompson
d2272c0620
Found and fixed the major architecture issue with the mig 7 used in the arty a7 board.
...
mig 7 is completely different from the ddr4 mig in that the internal pll does not general the required clocks. An external mmcm is required to general two inputs clocks and the required user clock.
2023-04-15 11:13:28 -05:00
Ross Thompson
c9445384d7
Realized we need a separate mmcm when using the mig 7 for ddr3 rather than the ddr4 mig. Go figure.
2023-04-14 18:02:16 -05:00
Ross Thompson
b5799c896e
Finally fixed the ddr3 mig script to work correclty.
2023-04-14 11:41:51 -05:00
