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I think the fpga is building again, but the debugger script needs to be updated. For some reason the nets are not present despite being marked debug.

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This commit is contained in:
Ross Thompson 2023-06-16 17:00:27 -05:00
parent 4bee446cad
commit 24b8c6c391
3 changed files with 366 additions and 365 deletions
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448
fpga/constraints/debug2.xdc
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278
fpga/constraints/debug4.xdc
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5
fpga/generator/wally.tcl
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@ -82,8 +82,9 @@ write_verilog -force -mode funcsim sim/syn-funcsim.v
if {$board=="ArtyA7"} {
source ../constraints/small-debug.xdc
} else {
source ../constraints/debug4.xdc
} else {
# *** RT: 16 June 2023 must add back in the debugger
#source ../constraints/debug4.xdc
}