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	Added probe script to generate a single probe for the fpga.
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							| @ -0,0 +1,74 @@ | ||||
| #!/usr/bin/python3 | ||||
| 
 | ||||
| import sys | ||||
| 
 | ||||
| def usage(): | ||||
|     print("Usage: ./probes name width probenum") | ||||
|     exit(1) | ||||
| 
 | ||||
| def header(): | ||||
|     return """create_debug_core u_ila_0 ila | ||||
| 
 | ||||
| set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0] | ||||
| set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] | ||||
| set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] | ||||
| set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] | ||||
| set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] | ||||
| set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] | ||||
| set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] | ||||
| set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] | ||||
| startgroup  | ||||
| set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ] | ||||
| set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ] | ||||
| set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ] | ||||
| set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ] | ||||
| endgroup | ||||
| connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]]""" | ||||
| 
 | ||||
| def convertLine(x): | ||||
|     temp = x.split() | ||||
|     temp[1] = int(temp[1]) | ||||
|     return tuple(temp) | ||||
| 
 | ||||
| def probeBits( probe ): | ||||
|     str = '' | ||||
| 
 | ||||
|     if (probe[1] > 1): | ||||
|         for i in range(probe[1]): | ||||
|             if i != (probe[1]-1): | ||||
|                 str = str + f"{{{probe[0]}[{i}]}} " | ||||
|             else: | ||||
|                 str = str + f"{{{probe[0]}[{i}]}} " | ||||
| 
 | ||||
|         else: | ||||
|             str = f'{{{probe[0]}}}' | ||||
| 
 | ||||
|     return str | ||||
| 
 | ||||
| def printProbe( probe, i ): | ||||
|     bits = probeBits(probe) | ||||
| 
 | ||||
|     return ( | ||||
|             f'create_debug_port u_ila_0 probe\n' | ||||
|             f'set_property port_width {probe[1]} [get_debug_ports u_ila_0/probe{i}]\n' | ||||
|             f'set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe{i}]\n' | ||||
|             f'connect_debug_port u_ila_0/probe{i} [get_nets [list {bits}]]\n\n' | ||||
|     ) | ||||
| 
 | ||||
| def main(args): | ||||
|     if (len(args) != 3): | ||||
|         usage() | ||||
| 
 | ||||
|     name = args[0] | ||||
|     width = int(args[1]) | ||||
|     probeNum = int(args[2]) | ||||
| 
 | ||||
| 
 | ||||
|     probe = (name, width) | ||||
| 
 | ||||
|     print(printProbe(probe, probeNum)) | ||||
| 
 | ||||
| if __name__ == '__main__': | ||||
|     main(sys.argv[1:]) | ||||
| 
 | ||||
|          | ||||
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