Commit Graph

20 Commits

Author SHA1 Message Date
David Harris
fa98ae8c30 Depricate conditional generation based on A_SUPPORTED, which is now computed from ZALRSC_SUPPORTED and ZAAMO_SUPPORTED 2024-08-08 05:27:35 -07:00
David Harris
f30cc46ec5 Disable misaligned accesses in imperas configuration and check misaligned support requires D$ 2024-07-21 08:26:07 -07:00
Ross Thompson
5e5ca0809f Removed more *** from lsu and updated assertions for dtim. 2024-06-19 10:52:51 -07:00
Jordan Carlin
1d8ffee20c
Certain Zcb instructions are dependent on other extensions, not the entire extension 2024-05-15 19:16:43 -07:00
Jordan Carlin
4ffce9a752
Switch riscvassertions to use bitwise operators instead of logical operators per Wally style guide 2024-05-15 09:23:24 -07:00
Jordan Carlin
291d1e62d5
M implies Zmmul 2024-05-14 19:38:34 -07:00
Jordan Carlin
4a72922087
update config to derive MISA from macros
- Remove C_SUPPORTED and update decompress unit based on Zc* extensions
- Derive A_SUPPORTED from A subextensions
- Derive B_SUPPORTED from B subextensions
- Derive C_SUPPORTED from C subextensions
2024-05-14 06:49:18 -07:00
David Harris
77137f0f60 ZAAMO and ZALRSC implemented but not tested 2024-05-07 16:45:49 -07:00
David Harris
2580d37fc0 ZK cleanup, check no LLEN > XLEN without D$, add half and quad float load/store to instruction name decoder 2024-03-10 22:03:57 -07:00
David Harris
efdc571f59 Removed redundant assertion 2024-02-01 20:14:40 -08:00
David Harris
49714cb282 Fixed assertions to throw fatal error, improved nightly regression to have passing cases 2024-01-31 21:39:18 -08:00
Rose Thompson
408bb2c35b Yay! I got verilator to compile our testbench! Does it actually work I don't know. 2023-12-18 16:44:34 -06:00
David Harris
28752303be Added ZCA/ZCF/ZCD/ZCB support. Doesn't break regression, but not tested. Need to get tests for Zcb. Draft tests are in riscv-arch-test but not yet committed there 2023-10-04 12:28:12 -07:00
David Harris
c6631ef808 Added N and PBMT bits to MMU PTE 2023-08-24 19:44:46 -07:00
David Harris
001d3cfdc5 Added logic to warn about x in memory reads. Added cbo instruction names to testbench decoder 2023-07-02 13:29:27 -07:00
David Harris
c2913f49a3 Added assertions for ZICNTR and ZIHPM 2023-06-16 09:26:02 -07:00
Ross Thompson
b8a243827b Found a whole bunch of files still using the old `define configurations. 2023-06-15 13:09:07 -05:00
David Harris
3678ab556c Removed unneeded diagnostic print 2023-03-03 16:46:16 -08:00
David Harris
cf8b5f0783 Added support for ZMMUL 2023-02-27 07:29:53 -08:00
David Harris
9d83749ca6 moved riscvassertons to its own file, added proper license headers to testbench support files 2023-02-16 19:40:27 -08:00