cturek
|
fb221d7b64
|
Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider.
|
2022-12-02 21:44:29 +00:00 |
|
cturek
|
04ac350a29
|
Added flops to preproc
|
2022-12-02 20:31:08 +00:00 |
|
David Harris
|
3a07d56d33
|
Renamed FPUStallD to FCvtIntStallD
|
2022-12-02 11:55:23 -08:00 |
|
David Harris
|
1b0f878c16
|
Renamed DivStartE to IFDivStartE
|
2022-12-02 11:30:49 -08:00 |
|
David Harris
|
db5f3c15a4
|
FPU divider working with execute stage stall
|
2022-12-02 11:11:53 -08:00 |
|
David Harris
|
a86c9de36b
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-12-02 04:28:50 -08:00 |
|
David Harris
|
6079a01bc8
|
update test list
|
2022-12-02 04:28:47 -08:00 |
|
Ross Thompson
|
602d191580
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-12-01 22:36:07 -06:00 |
|
David Harris
|
7c3e8553d1
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-12-01 16:27:36 -08:00 |
|
David Harris
|
0d23ab3ec1
|
reorder tests
|
2022-12-01 16:27:33 -08:00 |
|
Ross Thompson
|
3442b04f9e
|
Properly flush cacheLRU.
|
2022-12-01 17:32:58 -06:00 |
|
David Harris
|
3a8602523e
|
FPU test list
|
2022-12-01 10:18:36 -08:00 |
|
Ross Thompson
|
e403800ce8
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-12-01 11:47:54 -06:00 |
|
Ross Thompson
|
5025664cb0
|
Removed unused port on cacheway.
|
2022-12-01 11:47:48 -06:00 |
|
David Harris
|
28996d0b12
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-12-01 08:15:51 -08:00 |
|
David Harris
|
1bd639be6d
|
code cleanup
|
2022-12-01 08:15:48 -08:00 |
|
Ross Thompson
|
e6bd86f4fa
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-30 17:19:04 -06:00 |
|
David Harris
|
4ddc8fd603
|
signal sufixes in integer division
|
2022-11-30 15:15:37 -08:00 |
|
Ross Thompson
|
fa22484cfe
|
Reverted the IROM/DTIM address range modelsim assignment.
|
2022-11-30 17:13:33 -06:00 |
|
Ross Thompson
|
2f582cd91f
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-30 13:30:37 -06:00 |
|
Ross Thompson
|
a6355b1dcb
|
More optimization.
|
2022-11-30 11:26:48 -06:00 |
|
Ross Thompson
|
0aa7ce0b24
|
Removed reset on dirty cache bits.
|
2022-11-30 11:04:37 -06:00 |
|
Ross Thompson
|
cedb234013
|
Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now.
|
2022-11-30 11:01:25 -06:00 |
|
Ross Thompson
|
0454eb95ad
|
Preparing to merge dirty and tag srams.
|
2022-11-30 10:40:48 -06:00 |
|
Ross Thompson
|
de538d1c2f
|
Intermediate commit. Replaced flip flop dirty bit array with sram.
|
2022-11-30 00:08:31 -06:00 |
|
cturek
|
10c2d45888
|
div tests in sim-wally
|
2022-11-30 02:32:04 +00:00 |
|
Ross Thompson
|
453ea36512
|
Optimization of cacheway.
|
2022-11-29 18:30:47 -06:00 |
|
Ross Thompson
|
fbf543bf57
|
Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.
|
2022-11-29 17:19:31 -06:00 |
|
Ross Thompson
|
0277227323
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-29 14:57:38 -06:00 |
|
Ross Thompson
|
b5718c9baa
|
Fixed a bug with the replacement policy. It was updating the wrong set on load hits.
|
2022-11-29 14:51:09 -06:00 |
|
Ross Thompson
|
96cc4c7ebe
|
Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled.
|
2022-11-29 14:09:48 -06:00 |
|
Kip Macsai-Goren
|
c7c578c104
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-29 10:43:44 -08:00 |
|
Kip Macsai-Goren
|
44ea8d8b22
|
added failing satp invalid tests to regression
|
2022-11-29 10:43:38 -08:00 |
|
Ross Thompson
|
da82ab3712
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-29 11:52:35 -06:00 |
|
Ross Thompson
|
78acd40424
|
Renamed signals in the cache.
|
2022-11-29 10:52:40 -06:00 |
|
Kip Macsai-Goren
|
9b1765ce92
|
added tests for invalid address being written to satp. Not passing regression
|
2022-11-27 13:22:35 -08:00 |
|
Ross Thompson
|
6dd5668d21
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-22 18:07:32 -06:00 |
|
cturek
|
bdb9e24a66
|
Almost done with Int division
|
2022-11-22 22:22:59 +00:00 |
|
cturek
|
78c2ce5649
|
Updated testbench/wave for fdivsqrt new start signals
|
2022-11-22 22:22:26 +00:00 |
|
Ross Thompson
|
279f5bc615
|
Cleanup cacheLRU.
|
2022-11-22 14:59:01 -06:00 |
|
Ross Thompson
|
e1dbe58632
|
File name change for cachereplacement policy to cacheLRU
|
2022-11-20 22:35:02 -06:00 |
|
Ross Thompson
|
4e926ba4cf
|
Signal name changes for LRU.
|
2022-11-20 22:31:36 -06:00 |
|
Ross Thompson
|
e99a424ddc
|
Updated top level fpga file.
|
2022-11-18 11:10:45 -06:00 |
|
Ross Thompson
|
d67ba9e55a
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-17 17:45:59 -06:00 |
|
Ross Thompson
|
00218d559f
|
Missing a file. Last commit will fail.
|
2022-11-17 17:45:41 -06:00 |
|
Ross Thompson
|
47e1d1764b
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-17 17:38:52 -06:00 |
|
Ross Thompson
|
0106777f02
|
Finally have the correct replacement policy implementation.
|
2022-11-17 17:36:37 -06:00 |
|
Ross Thompson
|
70d7fca750
|
Updated fpga wave configuration.
|
2022-11-16 15:57:19 -06:00 |
|
Ross Thompson
|
6ad9ba1e73
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-16 15:39:17 -06:00 |
|
Ross Thompson
|
faa13a96e0
|
I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps.
|
2022-11-16 15:38:37 -06:00 |
|